1#! /usr/bin/env perl
2# This file is dual-licensed, meaning that you can use it under your
3# choice of either of the following two licenses:
4#
5# Copyright 2023 The OpenSSL Project Authors. All Rights Reserved.
6#
7# Licensed under the Apache License 2.0 (the "License"). You can obtain
8# a copy in the file LICENSE in the source distribution or at
9# https://www.openssl.org/source/license.html
10#
11# or
12#
13# Copyright (c) 2023, Christoph Müllner <christoph.muellner@vrull.eu>
14# Copyright (c) 2023, Phoebe Chen <phoebe.chen@sifive.com>
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions
19# are met:
20# 1. Redistributions of source code must retain the above copyright
21#    notice, this list of conditions and the following disclaimer.
22# 2. Redistributions in binary form must reproduce the above copyright
23#    notice, this list of conditions and the following disclaimer in the
24#    documentation and/or other materials provided with the distribution.
25#
26# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37
38# The generated code of this file depends on the following RISC-V extensions:
39# - RV64I
40# - RISC-V vector ('V') with VLEN >= 128
41# - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')
42# - RISC-V Vector SHA-2 Secure Hash extension ('Zvknhb')
43
44use strict;
45use warnings;
46
47use FindBin qw($Bin);
48use lib "$Bin";
49use lib "$Bin/../../perlasm";
50use riscv;
51
52# $output is the last argument if it looks like a file (it has an extension)
53# $flavour is the first argument if it doesn't look like a file
54my $output = $#ARGV >= 0 && $ARGV[$#ARGV] =~ m|\.\w+$| ? pop : undef;
55my $flavour = $#ARGV >= 0 && $ARGV[0] !~ m|\.| ? shift : undef;
56
57$output and open STDOUT,">$output";
58
59my $code=<<___;
60.text
61___
62
63my ($V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7,
64    $V8, $V9, $V10, $V11, $V12, $V13, $V14, $V15,
65    $V16, $V17, $V18, $V19, $V20, $V21, $V22, $V23,
66    $V24, $V25, $V26, $V27, $V28, $V29, $V30, $V31,
67) = map("v$_",(0..31));
68
69my $K512 = "K512";
70
71# Function arguments
72my ($H, $INP, $LEN, $KT, $H2, $INDEX_PATTERN) = ("a0", "a1", "a2", "a3", "t3", "t4");
73
74################################################################################
75# void sha512_block_data_order_zvkb_zvknhb(void *c, const void *p, size_t len)
76$code .= <<___;
77.p2align 2
78.globl sha512_block_data_order_zvkb_zvknhb
79.type sha512_block_data_order_zvkb_zvknhb,\@function
80sha512_block_data_order_zvkb_zvknhb:
81    @{[vsetivli "zero", 4, "e64", "m2", "ta", "ma"]}
82
83    # H is stored as {a,b,c,d},{e,f,g,h}, but we need {f,e,b,a},{h,g,d,c}
84    # The dst vtype is e64m2 and the index vtype is e8mf4.
85    # We use index-load with the following index pattern at v1.
86    #   i8 index:
87    #     40, 32, 8, 0
88    # Instead of setting the i8 index, we could use a single 32bit
89    # little-endian value to cover the 4xi8 index.
90    #   i32 value:
91    #     0x 00 08 20 28
92    li $INDEX_PATTERN, 0x00082028
93    @{[vsetivli "zero", 1, "e32", "m1", "ta", "ma"]}
94    @{[vmv_v_x $V1, $INDEX_PATTERN]}
95
96    addi $H2, $H, 16
97
98    # Use index-load to get {f,e,b,a},{h,g,d,c}
99    @{[vsetivli "zero", 4, "e64", "m2", "ta", "ma"]}
100    @{[vluxei8_v $V22, $H, $V1]}
101    @{[vluxei8_v $V24, $H2, $V1]}
102
103    # Setup v0 mask for the vmerge to replace the first word (idx==0) in key-scheduling.
104    # The AVL is 4 in SHA, so we could use a single e8(8 element masking) for masking.
105    @{[vsetivli "zero", 1, "e8", "m1", "ta", "ma"]}
106    @{[vmv_v_i $V0, 0x01]}
107
108    @{[vsetivli "zero", 4, "e64", "m2", "ta", "ma"]}
109
110L_round_loop:
111    # Load round constants K512
112    la $KT, $K512
113
114    # Decrement length by 1
115    addi $LEN, $LEN, -1
116
117    # Keep the current state as we need it later: H' = H+{a',b',c',...,h'}.
118    @{[vmv_v_v $V26, $V22]}
119    @{[vmv_v_v $V28, $V24]}
120
121    # Load the 1024-bits of the message block in v10-v16 and perform the endian
122    # swap.
123    @{[vle64_v $V10, $INP]}
124    @{[vrev8_v $V10, $V10]}
125    addi $INP, $INP, 32
126    @{[vle64_v $V12, $INP]}
127    @{[vrev8_v $V12, $V12]}
128    addi $INP, $INP, 32
129    @{[vle64_v $V14, $INP]}
130    @{[vrev8_v $V14, $V14]}
131    addi $INP, $INP, 32
132    @{[vle64_v $V16, $INP]}
133    @{[vrev8_v $V16, $V16]}
134    addi $INP, $INP, 32
135
136    .rept 4
137    # Quad-round 0 (+0, v10->v12->v14->v16)
138    @{[vle64_v $V20, ($KT)]}
139    addi $KT, $KT, 32
140    @{[vadd_vv $V18, $V20, $V10]}
141    @{[vsha2cl_vv $V24, $V22, $V18]}
142    @{[vsha2ch_vv $V22, $V24, $V18]}
143    @{[vmerge_vvm $V18, $V14, $V12, $V0]}
144    @{[vsha2ms_vv $V10, $V18, $V16]}
145
146    # Quad-round 1 (+1, v12->v14->v16->v10)
147    @{[vle64_v $V20, ($KT)]}
148    addi $KT, $KT, 32
149    @{[vadd_vv $V18, $V20, $V12]}
150    @{[vsha2cl_vv $V24, $V22, $V18]}
151    @{[vsha2ch_vv $V22, $V24, $V18]}
152    @{[vmerge_vvm $V18, $V16, $V14, $V0]}
153    @{[vsha2ms_vv $V12, $V18, $V10]}
154
155    # Quad-round 2 (+2, v14->v16->v10->v12)
156    @{[vle64_v $V20, ($KT)]}
157    addi $KT, $KT, 32
158    @{[vadd_vv $V18, $V20, $V14]}
159    @{[vsha2cl_vv $V24, $V22, $V18]}
160    @{[vsha2ch_vv $V22, $V24, $V18]}
161    @{[vmerge_vvm $V18, $V10, $V16, $V0]}
162    @{[vsha2ms_vv $V14, $V18, $V12]}
163
164    # Quad-round 3 (+3, v16->v10->v12->v14)
165    @{[vle64_v $V20, ($KT)]}
166    addi $KT, $KT, 32
167    @{[vadd_vv $V18, $V20, $V16]}
168    @{[vsha2cl_vv $V24, $V22, $V18]}
169    @{[vsha2ch_vv $V22, $V24, $V18]}
170    @{[vmerge_vvm $V18, $V12, $V10, $V0]}
171    @{[vsha2ms_vv $V16, $V18, $V14]}
172    .endr
173
174    # Quad-round 16 (+0, v10->v12->v14->v16)
175    # Note that we stop generating new message schedule words (Wt, v10-16)
176    # as we already generated all the words we end up consuming (i.e., W[79:76]).
177    @{[vle64_v $V20, ($KT)]}
178    addi $KT, $KT, 32
179    @{[vadd_vv $V18, $V20, $V10]}
180    @{[vsha2cl_vv $V24, $V22, $V18]}
181    @{[vsha2ch_vv $V22, $V24, $V18]}
182
183    # Quad-round 17 (+1, v12->v14->v16->v10)
184    @{[vle64_v $V20, ($KT)]}
185    addi $KT, $KT, 32
186    @{[vadd_vv $V18, $V20, $V12]}
187    @{[vsha2cl_vv $V24, $V22, $V18]}
188    @{[vsha2ch_vv $V22, $V24, $V18]}
189
190    # Quad-round 18 (+2, v14->v16->v10->v12)
191    @{[vle64_v $V20, ($KT)]}
192    addi $KT, $KT, 32
193    @{[vadd_vv $V18, $V20, $V14]}
194    @{[vsha2cl_vv $V24, $V22, $V18]}
195    @{[vsha2ch_vv $V22, $V24, $V18]}
196
197    # Quad-round 19 (+3, v16->v10->v12->v14)
198    @{[vle64_v $V20, ($KT)]}
199    # No t1 increment needed.
200    @{[vadd_vv $V18, $V20, $V16]}
201    @{[vsha2cl_vv $V24, $V22, $V18]}
202    @{[vsha2ch_vv $V22, $V24, $V18]}
203
204    # H' = H+{a',b',c',...,h'}
205    @{[vadd_vv $V22, $V26, $V22]}
206    @{[vadd_vv $V24, $V28, $V24]}
207    bnez $LEN, L_round_loop
208
209    # Store {f,e,b,a},{h,g,d,c} back to {a,b,c,d},{e,f,g,h}.
210    @{[vsuxei8_v $V22, ($H), $V1]}
211    @{[vsuxei8_v $V24, ($H2), $V1]}
212
213    ret
214.size sha512_block_data_order_zvkb_zvknhb,.-sha512_block_data_order_zvkb_zvknhb
215
216.p2align 3
217.type $K512,\@object
218$K512:
219    .dword 0x428a2f98d728ae22, 0x7137449123ef65cd
220    .dword 0xb5c0fbcfec4d3b2f, 0xe9b5dba58189dbbc
221    .dword 0x3956c25bf348b538, 0x59f111f1b605d019
222    .dword 0x923f82a4af194f9b, 0xab1c5ed5da6d8118
223    .dword 0xd807aa98a3030242, 0x12835b0145706fbe
224    .dword 0x243185be4ee4b28c, 0x550c7dc3d5ffb4e2
225    .dword 0x72be5d74f27b896f, 0x80deb1fe3b1696b1
226    .dword 0x9bdc06a725c71235, 0xc19bf174cf692694
227    .dword 0xe49b69c19ef14ad2, 0xefbe4786384f25e3
228    .dword 0x0fc19dc68b8cd5b5, 0x240ca1cc77ac9c65
229    .dword 0x2de92c6f592b0275, 0x4a7484aa6ea6e483
230    .dword 0x5cb0a9dcbd41fbd4, 0x76f988da831153b5
231    .dword 0x983e5152ee66dfab, 0xa831c66d2db43210
232    .dword 0xb00327c898fb213f, 0xbf597fc7beef0ee4
233    .dword 0xc6e00bf33da88fc2, 0xd5a79147930aa725
234    .dword 0x06ca6351e003826f, 0x142929670a0e6e70
235    .dword 0x27b70a8546d22ffc, 0x2e1b21385c26c926
236    .dword 0x4d2c6dfc5ac42aed, 0x53380d139d95b3df
237    .dword 0x650a73548baf63de, 0x766a0abb3c77b2a8
238    .dword 0x81c2c92e47edaee6, 0x92722c851482353b
239    .dword 0xa2bfe8a14cf10364, 0xa81a664bbc423001
240    .dword 0xc24b8b70d0f89791, 0xc76c51a30654be30
241    .dword 0xd192e819d6ef5218, 0xd69906245565a910
242    .dword 0xf40e35855771202a, 0x106aa07032bbd1b8
243    .dword 0x19a4c116b8d2d0c8, 0x1e376c085141ab53
244    .dword 0x2748774cdf8eeb99, 0x34b0bcb5e19b48a8
245    .dword 0x391c0cb3c5c95a63, 0x4ed8aa4ae3418acb
246    .dword 0x5b9cca4f7763e373, 0x682e6ff3d6b2b8a3
247    .dword 0x748f82ee5defb2fc, 0x78a5636f43172f60
248    .dword 0x84c87814a1f0ab72, 0x8cc702081a6439ec
249    .dword 0x90befffa23631e28, 0xa4506cebde82bde9
250    .dword 0xbef9a3f7b2c67915, 0xc67178f2e372532b
251    .dword 0xca273eceea26619c, 0xd186b8c721c0c207
252    .dword 0xeada7dd6cde0eb1e, 0xf57d4f7fee6ed178
253    .dword 0x06f067aa72176fba, 0x0a637dc5a2c898a6
254    .dword 0x113f9804bef90dae, 0x1b710b35131c471b
255    .dword 0x28db77f523047d84, 0x32caab7b40c72493
256    .dword 0x3c9ebe0a15c9bebc, 0x431d67c49c100d4c
257    .dword 0x4cc5d4becb3e42b6, 0x597f299cfc657e2a
258    .dword 0x5fcb6fab3ad6faec, 0x6c44198c4a475817
259.size $K512,.-$K512
260___
261
262print $code;
263
264close STDOUT or die "error closing STDOUT: $!";
265