Lines Matching refs:F3
76 #define F3(f) ((sljit_ins)(f) << 12) macro
80 #define ADD (F7(0x0) | F3(0x0) | OPC(0x33))
81 #define ADDI (F3(0x0) | OPC(0x13))
82 #define AND (F7(0x0) | F3(0x7) | OPC(0x33))
83 #define ANDI (F3(0x7) | OPC(0x13))
85 #define BEQ (F3(0x0) | OPC(0x63))
86 #define BNE (F3(0x1) | OPC(0x63))
87 #define BLT (F3(0x4) | OPC(0x63))
88 #define BGE (F3(0x5) | OPC(0x63))
89 #define BLTU (F3(0x6) | OPC(0x63))
90 #define BGEU (F3(0x7) | OPC(0x63))
91 #define DIV (F7(0x1) | F3(0x4) | OPC(0x33))
92 #define DIVU (F7(0x1) | F3(0x5) | OPC(0x33))
93 #define EBREAK (F12(0x1) | F3(0x0) | OPC(0x73))
94 #define FADD_S (F7(0x0) | F3(0x7) | OPC(0x53))
95 #define FDIV_S (F7(0xc) | F3(0x7) | OPC(0x53))
96 #define FEQ_S (F7(0x50) | F3(0x2) | OPC(0x53))
97 #define FLD (F3(0x3) | OPC(0x7))
98 #define FLE_S (F7(0x50) | F3(0x0) | OPC(0x53))
99 #define FLT_S (F7(0x50) | F3(0x1) | OPC(0x53))
104 #define FCVT_W_S (F7(0x60) | F3(0x1) | OPC(0x53))
105 #define FMUL_S (F7(0x8) | F3(0x7) | OPC(0x53))
106 #define FMV_X_W (F7(0x70) | F3(0x0) | OPC(0x53))
107 #define FMV_W_X (F7(0x78) | F3(0x0) | OPC(0x53))
108 #define FSD (F3(0x3) | OPC(0x27))
109 #define FSGNJ_S (F7(0x10) | F3(0x0) | OPC(0x53))
110 #define FSGNJN_S (F7(0x10) | F3(0x1) | OPC(0x53))
111 #define FSGNJX_S (F7(0x10) | F3(0x2) | OPC(0x53))
112 #define FSUB_S (F7(0x4) | F3(0x7) | OPC(0x53))
113 #define FSW (F3(0x2) | OPC(0x27))
115 #define JALR (F3(0x0) | OPC(0x67))
116 #define LD (F3(0x3) | OPC(0x3))
118 #define LW (F3(0x2) | OPC(0x3))
119 #define MUL (F7(0x1) | F3(0x0) | OPC(0x33))
120 #define MULH (F7(0x1) | F3(0x1) | OPC(0x33))
121 #define MULHU (F7(0x1) | F3(0x3) | OPC(0x33))
122 #define OR (F7(0x0) | F3(0x6) | OPC(0x33))
123 #define ORI (F3(0x6) | OPC(0x13))
124 #define REM (F7(0x1) | F3(0x6) | OPC(0x33))
125 #define REMU (F7(0x1) | F3(0x7) | OPC(0x33))
126 #define SD (F3(0x3) | OPC(0x23))
127 #define SLL (F7(0x0) | F3(0x1) | OPC(0x33))
128 #define SLLI (IMM_I(0x0) | F3(0x1) | OPC(0x13))
129 #define SLT (F7(0x0) | F3(0x2) | OPC(0x33))
130 #define SLTI (F3(0x2) | OPC(0x13))
131 #define SLTU (F7(0x0) | F3(0x3) | OPC(0x33))
132 #define SLTUI (F3(0x3) | OPC(0x13))
133 #define SRL (F7(0x0) | F3(0x5) | OPC(0x33))
134 #define SRLI (IMM_I(0x0) | F3(0x5) | OPC(0x13))
135 #define SRA (F7(0x20) | F3(0x5) | OPC(0x33))
136 #define SRAI (IMM_I(0x400) | F3(0x5) | OPC(0x13))
137 #define SUB (F7(0x20) | F3(0x0) | OPC(0x33))
138 #define SW (F3(0x2) | OPC(0x23))
139 #define XOR (F7(0x0) | F3(0x4) | OPC(0x33))
140 #define XORI (F3(0x4) | OPC(0x13))
947 /* u w s */ ARCH_32_64(F3(0x2) | OPC(0x23) /* sw */, F3(0x3) | OPC(0x23) /* sd */),
948 /* u w l */ ARCH_32_64(F3(0x2) | OPC(0x3) /* lw */, F3(0x3) | OPC(0x3) /* ld */),
949 /* u b s */ F3(0x0) | OPC(0x23) /* sb */,
950 /* u b l */ F3(0x4) | OPC(0x3) /* lbu */,
951 /* u h s */ F3(0x1) | OPC(0x23) /* sh */,
952 /* u h l */ F3(0x5) | OPC(0x3) /* lhu */,
953 /* u i s */ F3(0x2) | OPC(0x23) /* sw */,
954 /* u i l */ ARCH_32_64(F3(0x2) | OPC(0x3) /* lw */, F3(0x6) | OPC(0x3) /* lwu */),
956 /* s w s */ ARCH_32_64(F3(0x2) | OPC(0x23) /* sw */, F3(0x3) | OPC(0x23) /* sd */),
957 /* s w l */ ARCH_32_64(F3(0x2) | OPC(0x3) /* lw */, F3(0x3) | OPC(0x3) /* ld */),
958 /* s b s */ F3(0x0) | OPC(0x23) /* sb */,
959 /* s b l */ F3(0x0) | OPC(0x3) /* lb */,
960 /* s h s */ F3(0x1) | OPC(0x23) /* sh */,
961 /* s h l */ F3(0x1) | OPC(0x3) /* lh */,
962 /* s i s */ F3(0x2) | OPC(0x23) /* sw */,
963 /* s i l */ F3(0x2) | OPC(0x3) /* lw */,
965 /* d s */ F3(0x3) | OPC(0x27) /* fsd */,
966 /* d l */ F3(0x3) | OPC(0x7) /* fld */,
967 /* s s */ F3(0x2) | OPC(0x27) /* fsw */,
968 /* s l */ F3(0x2) | OPC(0x7) /* flw */,
2297 ins |= F3(0x7); in sljit_emit_fop1_conv_f64_from_sw()
2305 ins |= F3(0x7); in sljit_emit_fop1_conv_f64_from_sw()
2319 ins |= F3(0x7); in sljit_emit_fop1_conv_f64_from_uw()
2327 ins |= F3(0x7); in sljit_emit_fop1_conv_f64_from_uw()
2427 …FAIL_IF(push_inst(compiler, FCVT_S_D | ((op & SLJIT_32) ? (1 << 25) : ((1 << 20) | F3(7))) | FRD(d… in sljit_emit_fop1()
