Lines Matching refs:VORR
246 #define VORR 0xef200110 macro
3622 return push_inst32(compiler, VORR | ins); in sljit_emit_simd_mov()
3772 FAIL_IF(push_inst32(compiler, VORR | VD4(freg) | VN4(src) | VM4(src))); in sljit_emit_simd_replicate()
3777 return push_inst32(compiler, VORR | VD4(freg) | VN4(src) | VM4(src)); in sljit_emit_simd_replicate()
3871 FAIL_IF(push_inst32(compiler, VORR | VD4(freg) | VN4(srcdst) | VM4(srcdst))); in sljit_emit_simd_lane_mov()
3878 FAIL_IF(push_inst32(compiler, VORR | ins | VD4(TMP_FREG2) | VN4(freg) | VM4(freg))); in sljit_emit_simd_lane_mov()
3906 return push_inst32(compiler, VORR | VD4(srcdst) | VN4(freg) | VM4(freg)); in sljit_emit_simd_lane_mov()
3986 FAIL_IF(push_inst32(compiler, VORR | VD4(freg) | VN4(src) | VM4(src))); in sljit_emit_simd_lane_replicate()
3991 return push_inst32(compiler, VORR | VD4(freg) | VN4(src) | VM4(src)); in sljit_emit_simd_lane_replicate()
4049 return push_inst32(compiler, VORR | VD4(freg) | VN4(TMP_FREG2) | VM4(TMP_FREG2)); in sljit_emit_simd_extend()
4166 ins = VORR; in sljit_emit_simd_op2()
