Lines Matching refs:rule
1135 uint32_t rule = ir_rule(ctx, ref);
1142 switch (rule & IR_RULE_MASK) {
1145 if (rule & IR_FUSED) {
1167 if (rule & IR_FUSED) {
1242 if (!(rule & IR_FUSED)) {
1581 uint32_t rule = ctx->rules[addr_ref];
1583 if (!rule) {
1584 ctx->rules[addr_ref] = rule = ir_match_insn(ctx, addr_ref);
1586 if (rule >= IR_LEA_OB && rule <= IR_LEA_SI_B_O) {
1590 if (rule == IR_LEA_IB && ir_match_try_revert_lea_to_add(ctx, addr_ref)) {
1608 ctx->rules[addr_ref] = IR_FUSED | IR_SIMPLE | rule;
1640 uint32_t rule = ctx->rules[ref];
1644 if (rule == (IR_FUSED | IR_SIMPLE | IR_LEA_SI)) {
1646 } else if (!rule) {
1987 uint32_t rule = ctx->rules[insn->op1];
1989 if (!rule) {
1990 ctx->rules[insn->op1] = rule = ir_match_insn(ctx, insn->op1);
1992 if (rule == IR_LEA_SI || rule == (IR_FUSED | IR_SIMPLE | IR_LEA_SI)) {
1996 } else if (rule == IR_LEA_SIB || rule == (IR_FUSED | IR_SIMPLE | IR_LEA_SIB)) {
2000 } else if (rule == IR_LEA_IB || rule == (IR_FUSED | IR_SIMPLE | IR_LEA_IB)) {
2004 } else if (rule == IR_LEA_B_SI || rule == (IR_FUSED | IR_SIMPLE | IR_LEA_B_SI)) {
2007 } else if (rule == IR_LEA_SI_B || rule == (IR_FUSED | IR_SIMPLE | IR_LEA_SI_B)) {
2036 uint32_t rule =ctx->rules[insn->op1];
2037 if (!rule) {
2038 ctx->rules[insn->op1] = rule = ir_match_insn(ctx, insn->op1);
2040 if (rule == IR_LEA_OB) {
2043 rule = ctx->rules[insn->op2];
2044 if (!rule) {
2045 ctx->rules[insn->op2] = rule = ir_match_insn(ctx, insn->op2);
2047 if (rule == IR_LEA_SI || rule == (IR_FUSED | IR_SIMPLE | IR_LEA_SI)) {
2055 } else if (rule == IR_LEA_SI || rule == (IR_FUSED | IR_SIMPLE | IR_LEA_SI)) {
2058 rule = ctx->rules[insn->op2];
2059 if (!rule) {
2060 ctx->rules[insn->op2] = rule = ir_match_insn(ctx, insn->op2);
2062 if (rule == IR_LEA_OB || rule == (IR_FUSED | IR_SIMPLE | IR_LEA_OB)) {
2073 uint32_t rule = ctx->rules[insn->op2];
2074 if (!rule) {
2075 ctx->rules[insn->op2] = rule = ir_match_insn(ctx, insn->op2);
2077 if (rule == IR_LEA_OB || rule == (IR_FUSED | IR_SIMPLE | IR_LEA_OB)) {
2081 } else if (rule == IR_LEA_SI || rule == (IR_FUSED | IR_SIMPLE | IR_LEA_SI)) {
2346 uint32_t rule = ir_match_builtin_call(ctx, func);
2348 if (rule) {
2349 return rule;
2394 uint32_t rule = ctx->rules[insn->op3];
2396 if (!rule) {
2397 ctx->rules[insn->op3] = rule = ir_match_insn(ctx, insn->op3);
2399 …if (((rule & IR_RULE_MASK) == IR_BINOP_INT && op_insn->op != IR_MUL) || rule == IR_LEA_OB || rule …
2423 } else if (rule == IR_INC) {
2433 } else if (rule == IR_DEC) {
2443 } else if (rule == IR_MUL_PWR2) {
2453 } else if (rule == IR_DIV_PWR2) {
2463 } else if (rule == IR_MOD_PWR2) {
2473 } else if (rule == IR_SHIFT) {
2483 } else if (rule == IR_SHIFT_CONST) {
2493 } else if (rule == IR_OP_INT && op_insn->op != IR_BSWAP) {
2503 } else if (rule == IR_CMP_INT && load_op == IR_LOAD) {
2920 static void ir_match_insn2(ir_ctx *ctx, ir_ref ref, uint32_t rule)
2922 if (rule == IR_LEA_IB) {
3293 uint32_t rule = ctx->rules[ref];
3300 IR_ASSERT(((rule & IR_RULE_MASK) >= IR_LEA_OB &&
3301 (rule & IR_RULE_MASK) <= IR_LEA_SI_B_O) ||
3302 rule == IR_STATIC_ALLOCA);
3303 switch (rule & IR_RULE_MASK) {
4649 static void ir_emit_op_int(ir_ctx *ctx, ir_ref def, ir_insn *insn, uint32_t rule)
4671 if (rule == IR_INC) {
4673 } else if (rule == IR_DEC) {
4997 static void ir_emit_mem_op_int(ir_ctx *ctx, ir_ref def, ir_insn *insn, uint32_t rule)
5012 if (rule == IR_MEM_INC) {
5014 } else if (rule == IR_MEM_DEC) {
10098 uint32_t *rule, insn_flags;
10127 for (i = bb->start, insn = ctx->ir_base + i, rule = ctx->rules + i; i <= bb->end;) {
10128 switch (ctx->rules ? *rule : insn->op) {
10150 && *rule != IR_CMP_AND_BRANCH_INT
10151 && *rule != IR_CMP_AND_BRANCH_FP
10152 && *rule != IR_TEST_AND_BRANCH_INT
10153 && *rule != IR_GUARD_CMP_INT
10154 && *rule != IR_GUARD_CMP_FP) {
10282 rule += n;
10403 uint32_t *rule;
10515 rule = ctx->rules + i;
10518 if (!((*rule) & (IR_FUSED|IR_SKIPPED)))
10519 switch ((*rule) & IR_RULE_MASK) {
10570 ir_emit_op_int(ctx, i, insn, *rule);
10758 ir_emit_mem_op_int(ctx, i, insn, *rule);
10870 IR_ASSERT(0 && "NIY rule/instruction");
10880 rule += n;
