Lines Matching refs:op2
113 |.macro ASM_EXPAND_OP1_MEM, MACRO, op, type, op1, op2
121 | MACRO op, type, [offset], op2
123 | MACRO op, type, [Ra(base)+offset], op2
127 | MACRO op, type, [Ra(index)*8+offset], op2
129 | MACRO op, type, [Ra(base)+Ra(index)*8+offset], op2
133 | MACRO op, type, [Ra(index)*4+offset], op2
135 | MACRO op, type, [Ra(base)+Ra(index)*4+offset], op2
139 | MACRO op, type, [Ra(index)*2+offset], op2
141 | MACRO op, type, [Ra(base)+Ra(index)*2+offset], op2
146 | MACRO op, type, [Ra(index)+offset], op2
148 | MACRO op, type, [Ra(base)+Ra(index)+offset], op2
154 |.macro ASM_EXPAND_OP2_MEM, MACRO, op, type, op1, op2
156 || int32_t offset = IR_MEM_OFFSET(op2);
157 || int32_t base = IR_MEM_BASE(op2);
158 || int32_t index = IR_MEM_INDEX(op2);
159 || int32_t scale = IR_MEM_SCALE(op2);
195 |.macro ASM_EXPAND_OP2_MEM_3, MACRO, op, type, op1, op2, op3
197 || int32_t offset = IR_MEM_OFFSET(op2);
198 || int32_t base = IR_MEM_BASE(op2);
199 || int32_t index = IR_MEM_INDEX(op2);
200 || int32_t scale = IR_MEM_SCALE(op2);
236 |.macro ASM_EXPAND_OP3_MEM, MACRO, op, type, op1, op2, op3
244 | MACRO op, type, op1, op2, [offset]
246 | MACRO op, type, op1, op2, [Ra(base)+offset]
250 | MACRO op, type, op1, op2, [Ra(index)*8+offset]
252 | MACRO op, type, op1, op2, [Ra(base)+Ra(index)*8+offset]
256 | MACRO op, type, op1, op2, [Ra(index)*4+offset]
258 | MACRO op, type, op1, op2, [Ra(base)+Ra(index)*4+offset]
262 | MACRO op, type, op1, op2, [Ra(index)*2+offset]
264 | MACRO op, type, op1, op2, [Ra(base)+Ra(index)*2+offset]
269 | MACRO op, type, op1, op2, [Ra(index)+offset]
271 | MACRO op, type, op1, op2, [Ra(base)+Ra(index)+offset]
298 |.macro ASM_EXPAND_TYPE_MEM_REG, op, type, op1, op2
303 | op byte op1, Rb(op2)
306 | op word op1, Rw(op2)
309 | op dword op1, Rd(op2)
313 | op qword op1, Rq(op2)
319 |.macro ASM_EXPAND_TYPE_MEM_TXT, op, type, op1, op2
324 | op byte op1, op2
327 | op word op1, op2
330 | op dword op1, op2
334 | op qword op1, op2
340 |.macro ASM_EXPAND_TYPE_MEM_IMM, op, type, op1, op2
345 | op byte op1, (op2 & 0xff)
348 | op word op1, (op2 & 0xffff)
351 | op dword op1, op2
355 | op qword op1, op2
361 |.macro ASM_EXPAND_TYPE_REG_MEM, op, type, op1, op2
366 | op Rb(op1), byte op2
369 | op Rw(op1), word op2
372 | op Rd(op1), dword op2
376 | op Rq(op1), qword op2
423 |.macro ASM_TXT_TMEM_OP, op, op1, type, op2
425 || int32_t offset = IR_MEM_OFFSET(op2);
426 || int32_t base = IR_MEM_BASE(op2);
427 || int32_t index = IR_MEM_INDEX(op2);
428 || int32_t scale = IR_MEM_SCALE(op2);
464 |.macro ASM_TMEM_TXT_OP, op, type, op1, op2
472 | op type [offset], op2
474 | op type [Ra(base)+offset], op2
478 | op type [Ra(index)*8+offset], op2
480 | op type [Ra(base)+Ra(index)*8+offset], op2
484 | op type [Ra(index)*4+offset], op2
486 | op type [Ra(base)+Ra(index)*4+offset], op2
490 | op type [Ra(index)*2+offset], op2
492 | op type [Ra(base)+Ra(index)*2+offset], op2
497 | op type [Ra(index)+offset], op2
499 | op type [Ra(base)+Ra(index)+offset], op2
505 |.macro ASM_TXT_TXT_TMEM_OP, op, op1, op2, type, op3
513 | op op1, op2, type [offset]
515 | op op1, op2, type [Ra(base)+offset]
519 | op op1, op2, type [Ra(index)*8+offset]
521 | op op1, op2, type [Ra(base)+Ra(index)*8+offset]
525 | op op1, op2, type [Ra(index)*4+offset]
527 | op op1, op2, type [Ra(base)+Ra(index)*4+offset]
531 | op op1, op2, type [Ra(index)*2+offset]
533 | op op1, op2, type [Ra(base)+Ra(index)*2+offset]
538 | op op1, op2, type [Ra(index)+offset]
540 | op op1, op2, type [Ra(base)+Ra(index)+offset]
571 |.macro ASM_REG_REG_OP, op, type, op1, op2
576 | op Rb(op1), Rb(op2)
579 | op Rw(op1), Rw(op2)
582 | op Rd(op1), Rd(op2)
586 | op Rq(op1), Rq(op2)
592 |.macro ASM_REG_REG_OP2, op, type, op1, op2
598 | op Rw(op1), Rw(op2)
601 | op Rd(op1), Rd(op2)
605 | op Rq(op1), Rq(op2)
611 |.macro ASM_REG_TXT_OP, op, type, op1, op2
616 | op Rb(op1), op2
619 | op Rw(op1), op2
622 | op Rd(op1), op2
626 | op Rq(op1), op2
632 |.macro ASM_REG_IMM_OP, op, type, op1, op2
637 | op Rb(op1), (op2 & 0xff)
640 | op Rw(op1), (op2 & 0xffff)
643 | op Rd(op1), op2
647 | op Rq(op1), op2
653 |.macro ASM_MEM_REG_OP, op, type, op1, op2
654 | ASM_EXPAND_OP1_MEM ASM_EXPAND_TYPE_MEM_REG, op, type, op1, op2
657 |.macro ASM_MEM_TXT_OP, op, type, op1, op2
658 | ASM_EXPAND_OP1_MEM ASM_EXPAND_TYPE_MEM_TXT, op, type, op1, op2
661 |.macro ASM_MEM_IMM_OP, op, type, op1, op2
662 | ASM_EXPAND_OP1_MEM ASM_EXPAND_TYPE_MEM_IMM, op, type, op1, op2
665 |.macro ASM_REG_MEM_OP, op, type, op1, op2
666 | ASM_EXPAND_OP2_MEM ASM_REG_TXT_OP, op, type, op1, op2
669 |.macro ASM_REG_REG_MUL, op, type, op1, op2
674 | op Rw(op1), Rw(op2)
677 | op Rd(op1), Rd(op2)
681 | op Rq(op1), Rq(op2)
687 |.macro ASM_REG_IMM_MUL, op, type, op1, op2
692 | op Rw(op1), op2
695 | op Rd(op1), op2
699 | op Rq(op1), op2
705 |.macro ASM_REG_TXT_MUL, op, type, op1, op2
710 | op Rw(op1), op2
713 | op Rd(op1), op2
717 | op Rq(op1), op2
723 |.macro ASM_REG_MEM_MUL, op, type, op1, op2
724 | ASM_EXPAND_OP2_MEM ASM_REG_TXT_MUL, op, type, op1, op2
727 |.macro ASM_REG_TXT_TXT_MUL, op, type, op1, op2, op3
732 | op Rw(op1), op2, op3
735 | op Rd(op1), op2, op3
739 | op Rq(op1), op2, op3
745 |.macro ASM_REG_MEM_TXT_MUL, op, type, op1, op2, op3
746 | ASM_EXPAND_OP2_MEM_3 ASM_REG_TXT_TXT_MUL, imul, type, op1, op2, op3
749 |.macro ASM_SSE2_REG_REG_OP, op, type, op1, op2
751 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST)
754 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST)
758 |.macro ASM_SSE2_REG_TXT_OP, op, type, op1, op2
760 | op..d xmm(op1-IR_REG_FP_FIRST), qword op2
763 | op..s xmm(op1-IR_REG_FP_FIRST), dword op2
767 |.macro ASM_SSE2_REG_MEM_OP, op, type, op1, op2
768 | ASM_EXPAND_OP2_MEM ASM_SSE2_REG_TXT_OP, op, type, op1, op2
771 |.macro ASM_AVX_REG_REG_REG_OP, op, type, op1, op2, op3
773 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), xmm(op3-IR_REG_FP_FIRST)
776 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), xmm(op3-IR_REG_FP_FIRST)
780 |.macro ASM_AVX_REG_REG_TXT_OP, op, type, op1, op2, op3
782 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), qword op3
785 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), dword op3
789 |.macro ASM_AVX_REG_REG_MEM_OP, op, type, op1, op2, op3
790 | ASM_EXPAND_OP3_MEM ASM_AVX_REG_REG_TXT_OP, op, type, op1, op2, op3
793 |.macro ASM_FP_REG_REG_OP, op, type, op1, op2
795 | ASM_SSE2_REG_REG_OP v..op, type, op1, op2
797 | ASM_SSE2_REG_REG_OP op, type, op1, op2
818 |.macro ASM_FP_MEM_REG_OP, op, type, op1, op2
819 | ASM_EXPAND_OP1_MEM ASM_FP_TXT_REG_OP, op, type, op1, op2
822 |.macro ASM_FP_REG_TXT_OP, op, type, op1, op2
824 | ASM_SSE2_REG_TXT_OP v..op, type, op1, op2
826 | ASM_SSE2_REG_TXT_OP op, type, op1, op2
830 |.macro ASM_FP_REG_MEM_OP, op, type, op1, op2
832 | ASM_SSE2_REG_MEM_OP v..op, type, op1, op2
834 | ASM_SSE2_REG_MEM_OP op, type, op1, op2
838 |.macro ASM_SSE2_REG_REG_TXT_OP, op, type, op1, op2, op3
840 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), op3
843 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), op3
847 |.macro ASM_SSE2_REG_REG_REG_TXT_OP, op, type, op1, op2, op3, op4
849 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), xmm(op3-IR_REG_FP_FIRST), op4
852 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), xmm(op3-IR_REG_FP_FIRST), op4
856 |.macro ASM_FP_REG_REG_TXT_OP, op, type, op1, op2, op3
858 | ASM_SSE2_REG_REG_REG_TXT_OP v..op, type, op1, op2, op3
860 | ASM_SSE2_REG_REG_TXT_OP op, type, op1, op2, op3
1152 if (IR_IS_CONST_REF(insn->op2) && insn->op1 != insn->op2) {
1153 n = ir_add_const_tmp_reg(ctx, insn->op2, 2, n, constraints);
1154 } else if (ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA) {
1207 if (IR_IS_CONST_REF(insn->op2) && insn->op1 != insn->op2) {
1226 if (IR_IS_CONST_REF(insn->op2) && insn->op1 != insn->op2) {
1228 n = ir_add_const_tmp_reg(ctx, insn->op2, 2, n, constraints);
1229 } else if (ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA) {
1269 } else if (IR_IS_CONST_REF(insn->op2) || ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA) {
1296 if (IR_IS_CONST_REF(insn->op2)) {
1297 n = ir_add_const_tmp_reg(ctx, insn->op2, 2, n, constraints);
1329 if (IR_IS_CONST_REF(insn->op2)) {
1330 n = ir_add_const_tmp_reg(ctx, insn->op2, 2, n, constraints);
1336 if (IR_IS_CONST_REF(insn->op2)) {
1337 n = ir_add_const_tmp_reg(ctx, insn->op2, 2, n, constraints);
1348 if (IR_IS_CONST_REF(insn->op2)) {
1349 insn = &ctx->ir_base[insn->op2];
1374 if (!IR_IS_CONST_REF(insn->op2)) {
1397 int64_t offset = ctx->ir_base[insn->op2].val.u64 - 1;
1408 int64_t offset = ctx->ir_base[insn->op2].val.u64 - 1;
1421 int64_t offset = ctx->ir_base[insn->op2].val.u64 - 1;
1472 constraints->def_reg = ctx->ir_base[ref].op2;
1532 SWAP_REFS(insn->op1, insn->op2);
1540 if (insn->op1 == insn->op2) {
1542 } else if (ir_match_try_fuse_load(ctx, insn->op2, ref)) {
1595 if (IR_IS_CONST_REF(insn->op2)) {
1596 op2_insn = &ctx->ir_base[insn->op2];
1604 } else if (insn->op2 != ref) {
1607 } else if (insn->op2 == ref && insn->op1 != insn->op2) {
1627 && IR_IS_CONST_REF(insn->op2)) {
1628 insn = &ctx->ir_base[insn->op2];
1679 ir_ref addr_ref = ctx->ir_base[ref].op2;
1704 ir_ref addr_ref = ctx->ir_base[ref].op2;
1731 if (IR_IS_CONST_REF(insn->op2)
1732 && ir_may_fuse_imm(ctx, &ctx->ir_base[insn->op2])) {
1734 } else if (ir_match_try_fuse_load(ctx, insn->op2, root)) {
1743 if (!IR_IS_CONST_REF(insn->op2)
1744 && !ir_match_try_fuse_load(ctx, insn->op2, root)
1752 if (IR_IS_CONST_REF(insn->op2)
1753 && ir_may_fuse_imm(ctx, &ctx->ir_base[insn->op2])) {
1755 } else if (!ir_match_try_fuse_load(ctx, insn->op2, root)
1766 if (IR_IS_CONST_REF(insn->op2)
1767 && ir_may_fuse_imm(ctx, &ctx->ir_base[insn->op2])) {
1769 } else if (!ir_match_try_fuse_load(ctx, insn->op2, root)
1783 ir_match_fuse_load(ctx, insn->op2, root);
1784 } else if (IR_IS_CONST_REF(insn->op2) && !IR_IS_FP_ZERO(ctx->ir_base[insn->op2])) {
1786 } else if (ir_match_try_fuse_load(ctx, insn->op2, root)) {
1811 if (IR_IS_CONST_REF(insn->op2) && !IR_IS_FP_ZERO(ctx->ir_base[insn->op2])) {
1813 } else if (ir_match_try_fuse_load(ctx, insn->op2, root)) {
1910 if (IR_IS_CONST_REF(insn->op2)
1911 && !IR_IS_SYM_CONST(ctx->ir_base[insn->op2].op)
1912 && ctx->ir_base[insn->op2].val.i64 == 0
1930 ir_match_fuse_load(ctx, op1_insn->op2, ref);
1946 if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
1947 op2_insn = &ctx->ir_base[insn->op2];
2003 if (insn->op1 != insn->op2) {
2011 if (ctx->use_lists[insn->op2].count == 1 || ir_match_fuse_addr_all_useges(ctx, insn->op2)) {
2012 rule = ctx->rules[insn->op2];
2014 ctx->rules[insn->op2] = rule = ir_match_insn(ctx, insn->op2);
2018 ctx->rules[insn->op2] = IR_FUSED | IR_SIMPLE | IR_LEA_SI;
2026 if (ctx->use_lists[insn->op2].count == 1) {
2027 rule = ctx->rules[insn->op2];
2029 ctx->rules[insn->op2] = rule = ir_match_insn(ctx, insn->op2);
2033 ctx->rules[insn->op2] = IR_FUSED | IR_SIMPLE | IR_LEA_OB;
2041 if (ctx->use_lists[insn->op2].count == 1 || ir_match_fuse_addr_all_useges(ctx, insn->op2)) {
2042 uint32_t rule = ctx->rules[insn->op2];
2044 ctx->rules[insn->op2] = rule = ir_match_insn(ctx, insn->op2);
2047 ctx->rules[insn->op2] = IR_FUSED | IR_SIMPLE | IR_LEA_OB;
2051 ctx->rules[insn->op2] = IR_FUSED | IR_SIMPLE | IR_LEA_SI;
2065 ir_match_fuse_load(ctx, insn->op2, ref);
2078 ir_match_fuse_load(ctx, insn->op2, ref);
2089 if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
2090 op2_insn = &ctx->ir_base[insn->op2];
2124 ir_match_fuse_load(ctx, insn->op2, ref);
2137 if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
2138 op2_insn = &ctx->ir_base[insn->op2];
2149 ir_match_fuse_load(ctx, insn->op2, ref);
2153 if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
2154 op2_insn = &ctx->ir_base[insn->op2];
2170 ir_match_fuse_load(ctx, insn->op2, ref);
2177 if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
2178 op2_insn = &ctx->ir_base[insn->op2];
2192 ir_match_fuse_load(ctx, insn->op2, ref);
2217 if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
2218 op2_insn = &ctx->ir_base[insn->op2];
2231 if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
2232 op2_insn = &ctx->ir_base[insn->op2];
2245 if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
2246 op2_insn = &ctx->ir_base[insn->op2];
2255 if (IR_IS_CONST_REF(insn->op2)) {
2257 op2_insn = &ctx->ir_base[insn->op2];
2281 if (IR_IS_CONST_REF(insn->op2)) {
2283 op2_insn = &ctx->ir_base[insn->op2];
2311 if (IR_IS_CONST_REF(insn->op2)) {
2312 const ir_insn *func = &ctx->ir_base[insn->op2];
2331 ir_match_fuse_load(ctx, insn->op2, ref);
2340 if (IR_IS_CONST_REF(insn->op2) && ctx->cfg_map[ref] == 1) {
2341 ir_insn *val = &ctx->ir_base[insn->op2];
2371 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2376 if (!IR_IS_CONST_REF(op_insn->op2)
2377 && ctx->rules[op_insn->op2] == (IR_FUSED|IR_SIMPLE|IR_LOAD)) {
2378 ctx->rules[op_insn->op2] = IR_LOAD_INT;
2382 && insn->op1 == op_insn->op2
2383 && ctx->ir_base[op_insn->op2].op == load_op
2384 && ctx->ir_base[op_insn->op2].op2 == insn->op2
2385 && ctx->use_lists[op_insn->op2].count == 2) {
2395 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2405 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2415 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2425 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2435 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2445 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2455 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2465 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2484 ir_match_fuse_addr(ctx, insn->op2);
2492 ir_match_fuse_addr(ctx, insn->op2);
2502 if (IR_REGSET_IN(IR_REGSET_UNION((ir_regset)ctx->fixed_regset, IR_REGSET_FIXED), insn->op2)) {
2507 if (IR_IS_TYPE_INT(ctx->ir_base[insn->op2].type)) {
2509 && ir_in_same_block(ctx, insn->op2)
2510 && ctx->use_lists[insn->op2].count == 1
2511 && IR_IS_TYPE_INT(ctx->ir_base[insn->op2].type)) {
2512 ir_insn *op_insn = &ctx->ir_base[insn->op2];
2522 && ctx->ir_base[op_insn->op1].op2 == insn->op3
2525 ctx->rules[insn->op2] = IR_FUSED | IR_BINOP_INT;
2529 && insn->op1 == op_insn->op2
2530 && ctx->ir_base[op_insn->op2].op == IR_RLOAD
2531 && ctx->ir_base[op_insn->op2].op2 == insn->op3
2532 && ctx->use_lists[op_insn->op2].count == 2) {
2535 ctx->rules[insn->op2] = IR_FUSED | IR_BINOP_INT;
2542 ir_match_fuse_load(ctx, insn->op2, ref);
2555 if (!insn->op2) {
2557 } else if (IR_IS_TYPE_INT(ctx->ir_base[insn->op2].type)) {
2563 if (!IR_IS_CONST_REF(insn->op2) && ctx->use_lists[insn->op2].count == 1) {
2564 op2_insn = &ctx->ir_base[insn->op2];
2567 if (IR_IS_CONST_REF(op2_insn->op2)
2568 && !IR_IS_SYM_CONST(ctx->ir_base[op2_insn->op2].op)
2569 && ctx->ir_base[op2_insn->op2].val.i64 == 0
2570 && op2_insn->op1 == insn->op2 - 1) { /* previous instruction */
2577 ctx->rules[insn->op2] = IR_FUSED | IR_SIMPLE | IR_NOP;
2579 } else if (insn->op2 == ref - 1 && /* previous instruction */
2589 ir_match_fuse_load(ctx, op1_insn->op2, ref);
2592 ctx->rules[insn->op2] = IR_FUSED | IR_CMP_INT;
2598 ctx->rules[insn->op2] = IR_FUSED | IR_CMP_INT;
2603 ctx->rules[insn->op2] = IR_FUSED | IR_CMP_FP;
2609 ctx->rules[insn->op2] = IR_FUSED | IR_TEST_INT;
2611 } else if (op2_insn->op == IR_OVERFLOW && ir_in_same_block(ctx, insn->op2)) {
2613 ctx->rules[insn->op2] = IR_FUSED | IR_SIMPLE | IR_OVERFLOW;
2617 if (IR_IS_TYPE_INT(ctx->ir_base[insn->op2].type)) {
2618 if (insn->op2 == ref - 1) { /* previous instruction */
2619 op2_insn = &ctx->ir_base[insn->op2];
2630 ctx->rules[insn->op2] = IR_BINOP_INT | IR_MAY_SWAP;
2632 ir_match_fuse_load(ctx, op2_insn->op2, ref);
2633 ctx->rules[insn->op2] = IR_BINOP_INT;
2639 && insn->op2 == ref - 2 /* previous instruction */
2640 && ctx->use_lists[insn->op2].count == 2
2641 && IR_IS_TYPE_INT(ctx->ir_base[insn->op2].type)) {
2644 if (store_insn->op == IR_STORE && store_insn->op3 == insn->op2) {
2645 ir_insn *op_insn = &ctx->ir_base[insn->op2];
2654 && ctx->ir_base[op_insn->op1].op2 == store_insn->op2) {
2659 ctx->rules[insn->op2] = IR_FUSED | IR_BINOP_INT;
2661 ir_match_fuse_addr(ctx, store_insn->op2);
2666 && ctx->ir_base[op_insn->op2].op == IR_LOAD
2667 && ctx->ir_base[op_insn->op2].op2 == store_insn->op2) {
2668 if (ir_in_same_block(ctx, op_insn->op2)
2669 && ctx->use_lists[op_insn->op2].count == 2
2670 && store_insn->op1 == op_insn->op2) {
2673 ctx->rules[insn->op2] = IR_FUSED | IR_BINOP_INT;
2675 ir_match_fuse_addr(ctx, store_insn->op2);
2683 ir_match_fuse_load(ctx, insn->op2, ref);
2708 if (!IR_IS_CONST_REF(insn->op2) && ctx->use_lists[insn->op2].count == 1) {
2709 op2_insn = &ctx->ir_base[insn->op2];
2712 && (insn->op2 == ref - 1 ||
2713 (insn->op2 == ctx->prev_ref[ref] - 1
2716 if (IR_IS_CONST_REF(op2_insn->op2)
2717 && !IR_IS_SYM_CONST(ctx->ir_base[op2_insn->op2].op)
2718 && ctx->ir_base[op2_insn->op2].val.i64 == 0) {
2719 if (op2_insn->op1 == insn->op2 - 1) { /* previous instruction */
2730 ir_match_fuse_load(ctx, op1_insn->op2, ref);
2734 ctx->rules[insn->op2] = IR_FUSED | IR_CMP_INT;
2738 && op2_insn->op1 == insn->op2 - 2 /* before previous instruction */
2741 ir_insn *store_insn = &ctx->ir_base[insn->op2 - 1];
2751 && ctx->ir_base[op_insn->op1].op2 == store_insn->op2) {
2758 ir_match_fuse_addr(ctx, store_insn->op2);
2759 ctx->rules[insn->op2 - 1] = IR_MEM_BINOP_INT;
2760 ctx->rules[insn->op2] = IR_SKIPPED | IR_NOP;
2764 && ctx->ir_base[op_insn->op2].op == IR_LOAD
2765 && ctx->ir_base[op_insn->op2].op2 == store_insn->op2) {
2766 if (ir_in_same_block(ctx, op_insn->op2)
2767 && ctx->use_lists[op_insn->op2].count == 2
2768 && store_insn->op1 == op_insn->op2) {
2773 ir_match_fuse_addr(ctx, store_insn->op2);
2774 ctx->rules[insn->op2 - 1] = IR_MEM_BINOP_INT;
2775 ctx->rules[insn->op2] = IR_SKIPPED | IR_NOP;
2785 ctx->rules[insn->op2] = IR_FUSED | IR_CMP_INT;
2790 ctx->rules[insn->op2] = IR_FUSED | IR_CMP_FP;
2796 ctx->rules[insn->op2] = IR_FUSED | IR_TEST_INT;
2798 } else if (op2_insn->op == IR_OVERFLOW && ir_in_same_block(ctx, insn->op2)) {
2800 ctx->rules[insn->op2] = IR_FUSED | IR_SIMPLE | IR_OVERFLOW;
2804 ir_match_fuse_load(ctx, insn->op2, ref);
2837 if ((ctx->ir_base[insn->op2].op == IR_ALLOCA) || (ctx->ir_base[insn->op2].op == IR_VADDR)) {
2838 ir_use_list *use_list = &ctx->use_lists[insn->op2];
2844 if (use_insn->op3 == insn->op2) {
2848 if (use_insn->op2 == insn->op2) {
3283 scale = ctx->ir_base[insn->op2].val.i32;
3290 scale = ctx->ir_base[insn->op2].val.i32 - 1;
3299 } else if (ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA) {
3300 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
3315 if (ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA) {
3316 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
3331 op2_insn = &ctx->ir_base[insn->op2];
3338 index_reg_ref = insn->op2 * sizeof(ir_ref) + 1;
3346 index_reg_ref = insn->op2 * sizeof(ir_ref) + 1;
3352 scale = ctx->ir_base[op1_insn->op2].val.i32;
3359 scale = ctx->ir_base[op1_insn->op2].val.i32 - 1;
3369 index_reg_ref = insn->op2 * sizeof(ir_ref) + 1;
3372 op2_insn = &ctx->ir_base[insn->op2];
3373 scale = ctx->ir_base[op2_insn->op2].val.i32;
3385 scale = ctx->ir_base[op1_insn->op2].val.i32;
3386 op2_insn = &ctx->ir_base[insn->op2];
3393 base_reg_ref = insn->op2 * sizeof(ir_ref) + 1;
3404 index_reg_ref = insn->op2 * sizeof(ir_ref) + 1;
3405 op2_insn = &ctx->ir_base[insn->op2];
3406 scale = ctx->ir_base[op2_insn->op2].val.i32;
3411 if (ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA) {
3412 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
3419 scale = ctx->ir_base[op1_insn->op2].val.i32;
3432 ir_insn *addr_insn = &ctx->ir_base[offset_insn->op2];
3488 ir_emit_load(ctx, IR_ADDR, reg, mem_insn->op2);
3491 } else if (IR_IS_CONST_REF(mem_insn->op2)) {
3492 return ir_fuse_addr_const(ctx, mem_insn->op2);
3494 return ir_fuse_addr(ctx, root, mem_insn->op2);
3754 ir_ref op2 = insn->op2;
3771 if (op1 == op2) {
3779 if (op1 != op2) {
3780 ir_emit_load(ctx, type, op2_reg, op2);
3808 } else if (IR_IS_CONST_REF(op2)) {
3809 int32_t val = ir_fuse_imm(ctx, op2);
3839 if (ir_rule(ctx, op2) & IR_FUSED) {
3840 mem = ir_fuse_load(ctx, def, op2);
3842 mem = ir_ref_spill_slot(ctx, op2);
3881 ir_ref op2 = insn->op2;
3884 int32_t val = ir_fuse_imm(ctx, op2);
3930 ir_ref op2 = insn->op2;
3951 if (op1 != op2) {
3952 ir_emit_load(ctx, type, op2_reg, op2);
3956 if (op1 == op2) {
4004 ir_insn *overflow_insn = &ctx->ir_base[insn->op2];
4042 ir_ref op2 = op_insn->op2;
4050 mem = ir_var_spill_slot(ctx, insn->op2);
4054 int32_t val = ir_fuse_imm(ctx, op2);
4080 ir_emit_load(ctx, type, op2_reg, op2);
4110 ir_insn *op_insn = &ctx->ir_base[insn->op2];
4112 ir_ref op2 = op_insn->op2;
4113 ir_reg op2_reg = ctx->regs[insn->op2][2];
4120 int32_t val = ir_fuse_imm(ctx, op2);
4144 ir_emit_load(ctx, type, op2_reg, op2);
4177 IR_ASSERT(IR_IS_CONST_REF(insn->op2));
4178 IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[insn->op2].op));
4193 uint32_t shift = IR_LOG2(ctx->ir_base[insn->op2].val.u64);
4201 uint32_t shift = IR_LOG2(ctx->ir_base[insn->op2].val.u64);
4206 uint64_t mask = ctx->ir_base[insn->op2].val.u64 - 1;
4235 uint32_t shift = IR_LOG2(ctx->ir_base[insn->op2].val.u64);
4236 int64_t offset = ctx->ir_base[insn->op2].val.u64 - 1;
4239 IR_ASSERT(IR_IS_CONST_REF(insn->op2));
4240 IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[insn->op2].op));
4299 uint32_t shift = IR_LOG2(ctx->ir_base[insn->op2].val.u64);
4300 uint64_t mask = ctx->ir_base[insn->op2].val.u64 - 1;
4303 IR_ASSERT(IR_IS_CONST_REF(insn->op2));
4304 IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[insn->op2].op));
4360 IR_ASSERT(IR_IS_CONST_REF(op_insn->op2));
4361 IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[op_insn->op2].op));
4367 mem = ir_var_spill_slot(ctx, insn->op2);
4371 uint32_t shift = IR_LOG2(ctx->ir_base[op_insn->op2].val.u64);
4374 uint32_t shift = IR_LOG2(ctx->ir_base[op_insn->op2].val.u64);
4378 uint64_t mask = ctx->ir_base[op_insn->op2].val.u64 - 1;
4400 ir_emit_load(ctx, type, op2_reg, insn->op2);
4410 ir_emit_load(ctx, type, IR_REG_RCX, insn->op2);
4450 ir_ref op2 = op_insn->op2;
4458 mem = ir_var_spill_slot(ctx, insn->op2);
4463 ir_emit_load(ctx, type, op2_reg, op2);
4469 ir_emit_load(ctx, type, IR_REG_RCX, op2);
4503 IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[insn->op2].op));
4504 IR_ASSERT(IR_IS_SIGNED_32BIT(ctx->ir_base[insn->op2].val.i64));
4505 shift = ctx->ir_base[insn->op2].val.i32;
4552 IR_ASSERT(IR_IS_CONST_REF(op_insn->op2));
4553 IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[op_insn->op2].op));
4554 IR_ASSERT(IR_IS_SIGNED_32BIT(ctx->ir_base[op_insn->op2].val.i64));
4555 shift = ctx->ir_base[op_insn->op2].val.i32;
4560 mem = ir_var_spill_slot(ctx, insn->op2);
4944 mem = ir_var_spill_slot(ctx, insn->op2);
5021 ir_ref op2 = insn->op2;
5038 if (op2_reg == IR_REG_NONE && op1 == op2) {
5043 ir_emit_load(ctx, type, op2_reg, op2);
5045 } else if (IR_IS_CONST_REF(op2)
5048 ir_emit_load(ctx, type, op2_reg, op2);
5055 if (ir_rule(ctx, op2) & IR_FUSED) {
5056 mem = ir_fuse_load(ctx, def, op2);
5058 mem = ir_ref_spill_slot(ctx, op2);
5066 if (ir_rule(ctx, op2) & IR_FUSED) {
5067 mem = ir_fuse_load(ctx, def, op2);
5069 mem = ir_ref_spill_slot(ctx, op2);
5088 if (ir_rule(ctx, op2) & IR_FUSED) {
5089 mem = ir_fuse_load(ctx, def, op2);
5091 mem = ir_ref_spill_slot(ctx, op2);
5104 if (ir_rule(ctx, op2) & IR_FUSED) {
5105 mem = ir_fuse_load(ctx, def, op2);
5107 mem = ir_ref_spill_slot(ctx, op2);
5267 ir_ref op2 = insn->op2;
5284 if (op1 == op2) {
5291 if (op1 != op2) {
5292 ir_emit_load(ctx, type, op2_reg, op2);
5317 } else if (IR_IS_CONST_REF(op2)) {
5318 int label = ir_const_label(ctx, op2);
5345 if (ir_rule(ctx, op2) & IR_FUSED) {
5346 mem = ir_fuse_load(ctx, def, op2);
5348 mem = ir_ref_spill_slot(ctx, op2);
5384 ir_ref op2 = insn->op2;
5398 if (op1 != op2) {
5399 ir_emit_load(ctx, type, op2_reg, op2);
5424 } else if (IR_IS_CONST_REF(op2)) {
5425 int label = ir_const_label(ctx, op2);
5452 if (ir_rule(ctx, op2) & IR_FUSED) {
5453 mem = ir_fuse_load(ctx, def, op2);
5455 mem = ir_ref_spill_slot(ctx, op2);
5485 …, ir_type type, ir_ref root, ir_insn *insn, ir_reg op1_reg, ir_ref op1, ir_reg op2_reg, ir_ref op2)
5493 …} else if (IR_IS_CONST_REF(op2) && !IR_IS_SYM_CONST(ctx->ir_base[op2].op) && ctx->ir_base[op2].val…
5495 } else if (IR_IS_CONST_REF(op2)) {
5496 int32_t val = ir_fuse_imm(ctx, op2);
5501 if (ir_rule(ctx, op2) & IR_FUSED) {
5502 mem = ir_fuse_load(ctx, root, op2);
5504 mem = ir_ref_spill_slot(ctx, op2);
5521 int32_t val = ir_fuse_imm(ctx, op2);
5531 ir_ref op2 = cmp_insn->op2;
5541 if (op1 != op2) {
5542 ir_emit_load(ctx, type, op2_reg, op2);
5546 ir_emit_cmp_int_common(ctx, type, root, cmp_insn, op1_reg, op1, op2_reg, op2);
5639 ir_ref op2 = insn->op2;
5651 if (op1 != op2) {
5652 ir_emit_load(ctx, type, op2_reg, op2);
5655 …if (IR_IS_CONST_REF(op2) && !IR_IS_SYM_CONST(ctx->ir_base[op2].op) && ctx->ir_base[op2].val.u64 ==…
5676 ir_emit_cmp_int_common(ctx, type, def, insn, op1_reg, op1, op2_reg, op2);
5690 ir_ref op2 = binop_insn->op2;
5703 if (op1 != op2) {
5704 ir_emit_load(ctx, type, op2_reg, op2);
5708 } else if (IR_IS_CONST_REF(op2)) {
5709 int32_t val = ir_fuse_imm(ctx, op2);
5735 if (ir_rule(ctx, op2) & IR_FUSED) {
5736 mem = ir_fuse_load(ctx, root, op2);
5738 mem = ir_ref_spill_slot(ctx, op2);
5755 if (op1 != op2) {
5756 ir_emit_load(ctx, type, op2_reg, op2);
5762 int32_t val = ir_fuse_imm(ctx, op2);
5797 ir_ref op1, op2;
5801 op2 = cmp_insn->op2;
5808 SWAP_REFS(op1, op2);
5823 if (op1 != op2) {
5824 ir_emit_load(ctx, type, op2_reg, op2);
5828 } else if (IR_IS_CONST_REF(op2)) {
5829 int label = ir_const_label(ctx, op2);
5835 if (ir_rule(ctx, op2) & IR_FUSED) {
5836 mem = ir_fuse_load(ctx, root, op2);
5838 mem = ir_ref_spill_slot(ctx, op2);
6051 ir_insn *cmp_insn = &ctx->ir_base[insn->op2];
6055 ir_ref op2 = cmp_insn->op2;
6056 ir_reg op1_reg = ctx->regs[insn->op2][1];
6057 ir_reg op2_reg = ctx->regs[insn->op2][2];
6065 if (op1 != op2) {
6066 ir_emit_load(ctx, type, op2_reg, op2);
6069 …if (IR_IS_CONST_REF(op2) && !IR_IS_SYM_CONST(ctx->ir_base[op2].op) && ctx->ir_base[op2].val.u64 ==…
6090 prev_insn = &ctx->ir_base[prev_insn->op2];
6091 if (prev_insn->op1 == cmp_insn->op1 && prev_insn->op2 == cmp_insn->op2) {
6097 ir_emit_cmp_int_common(ctx, type, def, cmp_insn, op1_reg, op1, op2_reg, op2);
6104 ir_ref op2 = insn->op2;
6105 ir_op op = ctx->ir_base[op2].op;
6108 op2 = ctx->ir_base[op2].op1;
6114 ir_emit_test_int_common(ctx, def, op2, op);
6120 ir_op op = ir_emit_cmp_fp_common(ctx, def, insn->op2, &ctx->ir_base[insn->op2]);
6126 ir_type type = ctx->ir_base[insn->op2].type;
6134 ir_emit_load(ctx, type, op2_reg, insn->op2);
6137 } else if (IR_IS_CONST_REF(insn->op2)) {
6141 if (ir_const_is_true(&ctx->ir_base[insn->op2])) {
6151 } else if (ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA) {
6162 if (ir_rule(ctx, insn->op2) & IR_FUSED) {
6163 mem = ir_fuse_load(ctx, def, insn->op2);
6165 mem = ir_ref_spill_slot(ctx, insn->op2);
6178 ir_ref op2 = insn->op2;
6190 ir_emit_load(ctx, type, op2_reg, op2);
6191 if (op1 == op2) {
6194 if (op3 == op2) {
6198 if (op3_reg != IR_REG_NONE && op3 != op2 && IR_REG_SPILLED(op3_reg)) {
6201 if (op1 == op2) {
6205 if (op1_reg != IR_REG_NONE && op1 != op2 && op1 != op3 && IR_REG_SPILLED(op1_reg)) {
6233 } else if (IR_IS_CONST_REF(op2) && !IR_IS_SYM_CONST(ctx->ir_base[op2].op)) {
6235 ir_emit_mov_imm_int(ctx, type, def_reg, ctx->ir_base[op2].val.i64);
6237 ir_emit_load_ex(ctx, type, def_reg, op2, def);
6282 ir_emit_load_ex(ctx, type, def_reg, op2, def);
6309 ir_ref op2 = insn->op2;
6318 ir_emit_load(ctx, type, op2_reg, op2);
6319 if (op3 == op2) {
6323 if (op3_reg != IR_REG_NONE && op3 != op2 && IR_REG_SPILLED(op3_reg)) {
6346 } else if (IR_IS_CONST_REF(op2) && !IR_IS_SYM_CONST(ctx->ir_base[op2].op)) {
6348 ir_emit_mov_imm_int(ctx, type, def_reg, ctx->ir_base[op2].val.i64);
6350 ir_emit_load_ex(ctx, type, def_reg, op2, def);
6445 ir_emit_load_ex(ctx, type, def_reg, op2, def);
6473 ir_ref op2 = insn->op2;
6482 ir_emit_load(ctx, type, op2_reg, op2);
6483 if (op3 == op2) {
6487 if (op3_reg != IR_REG_NONE && op3 != op2 && IR_REG_SPILLED(op3_reg)) {
6545 ir_emit_load_ex(ctx, type, def_reg, op2, def);
6589 ir_type type = ctx->ir_base[insn->op2].type;
6594 ir_emit_load(ctx, type, IR_REG_INT_RET1, insn->op2);
6603 ir_type type = ctx->ir_base[insn->op2].type;
6610 ir_emit_load(ctx, type, IR_REG_FP_RET1, insn->op2);
6619 int32_t offset = ir_ref_spill_slot_offset(ctx, insn->op2, &fp);
7460 ir_insn *var_insn = &ctx->ir_base[insn->op2];
7482 ir_insn *var_insn = &ctx->ir_base[insn->op2];
7512 ir_insn *var_insn = &ctx->ir_base[insn->op2];
7554 IR_ASSERT(ctx->ir_base[insn->op2].type == IR_ADDR);
7555 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
7558 } else if (IR_IS_CONST_REF(insn->op2)) {
7559 mem = ir_fuse_addr_const(ctx, insn->op2);
7561 IR_ASSERT(ir_rule(ctx, insn->op2) & IR_FUSED);
7562 mem = ir_fuse_addr(ctx, def, insn->op2);
7593 IR_ASSERT(ctx->ir_base[insn->op2].type == IR_ADDR);
7594 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
7597 } else if (IR_IS_CONST_REF(insn->op2)) {
7598 mem = ir_fuse_addr_const(ctx, insn->op2);
7600 IR_ASSERT(ir_rule(ctx, insn->op2) & IR_FUSED);
7601 mem = ir_fuse_addr(ctx, def, insn->op2);
7628 IR_ASSERT(ctx->ir_base[insn->op2].type == IR_ADDR);
7629 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
7632 } else if (IR_IS_CONST_REF(insn->op2)) {
7633 mem = ir_fuse_addr_const(ctx, insn->op2);
7635 IR_ASSERT(ir_rule(ctx, insn->op2) & IR_FUSED);
7636 mem = ir_fuse_addr(ctx, ref, insn->op2);
7670 ir_ref op2 = cmp_insn->op2;
7677 IR_ASSERT(ctx->ir_base[insn->op2].type == IR_ADDR);
7678 ir_emit_load(ctx, IR_ADDR, addr_reg, insn->op2);
7681 } else if (IR_IS_CONST_REF(insn->op2)) {
7682 mem = ir_fuse_addr_const(ctx, insn->op2);
7684 IR_ASSERT(ir_rule(ctx, insn->op2) & IR_FUSED);
7685 mem = ir_fuse_addr(ctx, ref, insn->op2);
7694 if (op1 != op2) {
7695 ir_emit_load(ctx, type, op2_reg, op2);
7699 ir_emit_cmp_int_common(ctx, type, ref, cmp_insn, op1_reg, op1, op2_reg, op2);
7714 IR_ASSERT(ctx->ir_base[insn->op2].type == IR_ADDR);
7715 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
7718 } else if (IR_IS_CONST_REF(insn->op2)) {
7719 mem = ir_fuse_addr_const(ctx, insn->op2);
7721 IR_ASSERT(ir_rule(ctx, insn->op2) & IR_FUSED);
7722 mem = ir_fuse_addr(ctx, ref, insn->op2);
7750 ir_reg src_reg = insn->op2;
7788 ir_ref type = ctx->ir_base[insn->op2].type;
7795 ir_emit_load(ctx, type, op2_reg, insn->op2);
7806 ir_emit_load_ex(ctx, type, dst_reg, insn->op2, ref);
7820 if (IR_IS_CONST_REF(insn->op2)) {
7821 ir_insn *val = &ctx->ir_base[insn->op2];
7838 ir_type type = ctx->ir_base[insn->op2].type;
7845 ir_emit_load(ctx, type, op2_reg, insn->op2);
7851 ir_emit_load(ctx, type, def_reg, insn->op2);
7874 if (IR_IS_CONST_REF(insn->op2)) {
7875 ir_insn *val = &ctx->ir_base[insn->op2];
7892 ir_type type = ctx->ir_base[insn->op2].type;
7897 ir_emit_load(ctx, type, op2_reg, insn->op2);
7928 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
7965 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
7969 IR_ASSERT(ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA);
7971 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
7999 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
8003 IR_ASSERT(ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA);
8005 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
8066 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
8070 IR_ASSERT(ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA);
8072 op2_offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
8100 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
8104 IR_ASSERT(ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA);
8106 op2_offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
8148 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
8152 IR_ASSERT(ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA);
8154 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
8177 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
8181 IR_ASSERT(ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA);
8183 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
8239 type = ctx->ir_base[insn->op2].type;
8255 val = &ctx->ir_base[use_insn->op2];
8276 ir_emit_load(ctx, type, op2_reg, insn->op2);
8291 val = &ctx->ir_base[use_insn->op2];
8399 if (insn->op == IR_IJMP && IR_IS_CONST_REF(insn->op2)) {
8405 void *addr = ir_jmp_addr(ctx, insn, &ctx->ir_base[insn->op2]);
8427 val = &ctx->ir_base[use_insn->op2];
8776 if (IR_IS_CONST_REF(insn->op2)) {
8777 void *addr = ir_call_addr(ctx, insn, &ctx->ir_base[insn->op2]);
8804 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
8810 if (ir_rule(ctx, insn->op2) & IR_FUSED) {
8811 mem = ir_fuse_load(ctx, def, insn->op2);
8813 mem = ir_ref_spill_slot(ctx, insn->op2);
8916 if (IR_IS_CONST_REF(insn->op2)) {
8917 void *addr = ir_call_addr(ctx, insn, &ctx->ir_base[insn->op2]);
8944 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
8950 if (ir_rule(ctx, insn->op2) & IR_FUSED) {
8951 mem = ir_fuse_load(ctx, def, insn->op2);
8953 mem = ir_ref_spill_slot(ctx, insn->op2);
8966 if (IR_IS_CONST_REF(insn->op2)) {
8967 void *addr = ir_jmp_addr(ctx, insn, &ctx->ir_base[insn->op2]);
8981 } else if (ir_rule(ctx, insn->op2) & IR_FUSED) {
8982 ir_mem mem = ir_fuse_load(ctx, def, insn->op2);
8987 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
8991 ir_mem mem = ir_ref_spill_slot(ctx, insn->op2);
9087 } else if (next_insn->op == IR_IJMP && IR_IS_CONST_REF(next_insn->op2)) {
9088 void *target_addr = ir_jmp_addr(ctx, next_insn, &ctx->ir_base[next_insn->op2]);
9237 ir_type type = ctx->ir_base[insn->op2].type;
9241 if (IR_IS_CONST_REF(insn->op2)) {
9242 bool is_true = ir_ref_is_true(ctx, insn->op2);
9265 ir_emit_load(ctx, type, op2_reg, insn->op2);
9271 if (ir_rule(ctx, insn->op2) & IR_FUSED) {
9272 mem = ir_fuse_load(ctx, def, insn->op2);
9274 mem = ir_ref_spill_slot(ctx, insn->op2);
9314 ir_insn *cmp_insn = &ctx->ir_base[insn->op2];
9318 ir_ref op2 = cmp_insn->op2;
9319 ir_reg op1_reg = ctx->regs[insn->op2][1];
9320 ir_reg op2_reg = ctx->regs[insn->op2][2];
9329 if (op1 != op2) {
9330 ir_emit_load(ctx, type, op2_reg, op2);
9335 …if (IR_IS_CONST_REF(op2) && !IR_IS_SYM_CONST(ctx->ir_base[op2].op) && ctx->ir_base[op2].val.u64 ==…
9360 ir_emit_cmp_int_common(ctx, type, def, cmp_insn, op1_reg, op1, op2_reg, op2);
9371 ir_op op = ir_emit_cmp_fp_common(ctx, def, insn->op2, &ctx->ir_base[insn->op2]);
9385 ir_emit_test_int_common(ctx, def, insn->op2, op);
9392 ir_op op = ctx->ir_base[insn->op2].op;
9407 type = ctx->ir_base[ctx->ir_base[insn->op2].op1].type;
9486 | mov Ra(reg), aword [Ra(reg)+insn->op2]
9491 | mov Ra(reg), aword [Ra(reg)+insn->op2]
9496 | mov Ra(reg), aword [insn->op2]
9498 | mov Ra(reg), aword [insn->op2]
9504 | mov Ra(reg), aword [insn->op2]
9507 | mov Ra(reg), aword [Ra(reg)+insn->op2]
9513 | mov Ra(reg), aword [insn->op2]
9516 | mov Ra(reg), aword [Ra(reg)+insn->op2]
9646 if (IR_IS_CONST_REF(insn->op2)) {
9647 void *addr = ir_call_addr(ctx, insn, &ctx->ir_base[insn->op2]);
10481 ir_op op = ctx->ir_base[insn->op2].op;
