Lines Matching refs:reg
35 bool ir_reg_is_int(int32_t reg) in ir_reg_is_int() argument
37 IR_ASSERT(reg >= 0 && reg < IR_REG_NUM); in ir_reg_is_int()
38 return reg >= IR_REG_GP_FIRST && reg <= IR_REG_GP_LAST; in ir_reg_is_int()
123 ival->reg = IR_REG_NONE; in ir_new_live_range()
225 static void ir_add_fixed_live_range(ir_ctx *ctx, ir_reg reg, ir_live_pos start, ir_live_pos end) in ir_add_fixed_live_range() argument
227 int v = ctx->vregs_count + 1 + reg; in ir_add_fixed_live_range()
234 ival->reg = reg; in ir_add_fixed_live_range()
272 ival->reg = IR_REG_NONE; in ir_add_tmp()
507 ir_reg reg; in ir_add_fusion_ranges() local
523 ir_add_fixed_live_range(ctx, constraints.tmp_regs[n].reg, in ir_add_fusion_ranges()
550 reg = (j < constraints.hints_count) ? constraints.hints[j] : IR_REG_NONE; in ir_add_fusion_ranges()
552 if (EXPECTED(reg == IR_REG_NONE)) { in ir_add_fusion_ranges()
565 ir_add_use(ctx, ival, j, use_pos, reg, use_flags, -input); in ir_add_fusion_ranges()
741 ir_add_fixed_live_range(ctx, constraints.tmp_regs[n].reg, in ir_compute_live_ranges()
760 ir_reg reg = constraints.def_reg; in ir_compute_live_ranges() local
762 if (reg != IR_REG_NONE) { in ir_compute_live_ranges()
766 ir_add_fixed_live_range(ctx, reg, IR_START_LIVE_POS_FROM_REF(bb->start), def_pos); in ir_compute_live_ranges()
791 ir_add_use(ctx, ival, 0, def_pos, reg, def_flags, hint_ref); in ir_compute_live_ranges()
817 ir_reg reg = (j < constraints.hints_count) ? constraints.hints[j] : IR_REG_NONE; in ir_compute_live_ranges() local
826 if (reg != IR_REG_NONE) { in ir_compute_live_ranges()
828 ir_add_fixed_live_range(ctx, reg, use_pos, use_pos + IR_USE_SUB_REF); in ir_compute_live_ranges()
847 ir_add_use(ctx, ival, j, use_pos, reg, IR_USE_FLAGS(def_flags, j), hint_ref); in ir_compute_live_ranges()
855 } else if (reg != IR_REG_NONE) { in ir_compute_live_ranges()
857 ir_add_fixed_live_range(ctx, reg, use_pos, use_pos + IR_USE_SUB_REF); in ir_compute_live_ranges()
1163 ir_reg reg; in ir_add_fusion_ranges() local
1180 ir_add_fixed_live_range(ctx, constraints.tmp_regs[n].reg, in ir_add_fusion_ranges()
1207 reg = (j < constraints.hints_count) ? constraints.hints[j] : IR_REG_NONE; in ir_add_fusion_ranges()
1209 if (EXPECTED(reg == IR_REG_NONE)) { in ir_add_fusion_ranges()
1223 ir_add_use(ctx, ival, j, use_pos, reg, use_flags, -input); in ir_add_fusion_ranges()
1359 ir_add_fixed_live_range(ctx, constraints.tmp_regs[n].reg, in ir_compute_live_ranges()
1376 ir_reg reg = constraints.def_reg; in ir_compute_live_ranges() local
1378 if (reg != IR_REG_NONE) { in ir_compute_live_ranges()
1382 ir_add_fixed_live_range(ctx, reg, IR_START_LIVE_POS_FROM_REF(bb->start), def_pos); in ir_compute_live_ranges()
1409 ir_add_use(ctx, ival, 0, def_pos, reg, def_flags, hint_ref); in ir_compute_live_ranges()
1433 ir_reg reg = (j < constraints.hints_count) ? constraints.hints[j] : IR_REG_NONE; in ir_compute_live_ranges() local
1442 if (reg != IR_REG_NONE) { in ir_compute_live_ranges()
1444 ir_add_fixed_live_range(ctx, reg, use_pos, use_pos + IR_USE_SUB_REF); in ir_compute_live_ranges()
1467 ir_add_use(ctx, ival, j, use_pos, reg, IR_USE_FLAGS(def_flags, j), hint_ref); in ir_compute_live_ranges()
1475 if (reg != IR_REG_NONE) { in ir_compute_live_ranges()
1477 ir_add_fixed_live_range(ctx, reg, use_pos, use_pos + IR_USE_SUB_REF); in ir_compute_live_ranges()
1481 } else if (reg != IR_REG_NONE) { in ir_compute_live_ranges()
1483 ir_add_fixed_live_range(ctx, reg, use_pos, use_pos + IR_USE_SUB_REF); in ir_compute_live_ranges()
2246 ir_reg_name(_ival->reg, _ival->type)); \
2272 ir_reg_name(_ival->reg, _ival->type), \
2471 child->reg = IR_REG_NONE; in ir_split_interval_at()
2644 ir_reg reg; in ir_get_first_reg_hint() local
2648 reg = use_pos->hint; in ir_get_first_reg_hint()
2649 if (reg >= 0 && IR_REGSET_IN(available, reg)) { in ir_get_first_reg_hint()
2650 return reg; in ir_get_first_reg_hint()
2661 ir_reg reg; in ir_try_allocate_preferred_reg() local
2666 reg = use_pos->hint; in ir_try_allocate_preferred_reg()
2667 if (reg >= 0 && IR_REGSET_IN(available, reg)) { in ir_try_allocate_preferred_reg()
2668 if (ival->end <= freeUntilPos[reg]) { in ir_try_allocate_preferred_reg()
2670 return reg; in ir_try_allocate_preferred_reg()
2681 reg = ctx->live_intervals[ctx->vregs[use_pos->hint_ref]]->reg; in ir_try_allocate_preferred_reg()
2682 if (reg >= 0 && IR_REGSET_IN(available, reg)) { in ir_try_allocate_preferred_reg()
2683 if (ival->end <= freeUntilPos[reg]) { in ir_try_allocate_preferred_reg()
2685 return reg; in ir_try_allocate_preferred_reg()
2699 ir_reg reg; in ir_get_preferred_reg() local
2703 reg = use_pos->hint; in ir_get_preferred_reg()
2704 if (reg >= 0 && IR_REGSET_IN(available, reg)) { in ir_get_preferred_reg()
2705 return reg; in ir_get_preferred_reg()
2707 reg = ctx->live_intervals[ctx->vregs[use_pos->hint_ref]]->reg; in ir_get_preferred_reg()
2708 if (reg >= 0 && IR_REGSET_IN(available, reg)) { in ir_get_preferred_reg()
2709 return reg; in ir_get_preferred_reg()
2811 int i, reg; in ir_try_allocate_free_reg() local
2847 reg = other->reg; in ir_try_allocate_free_reg()
2848 IR_ASSERT(reg >= 0); in ir_try_allocate_free_reg()
2849 if (reg >= IR_REG_SCRATCH) { in ir_try_allocate_free_reg()
2850 if (reg == IR_REG_SCRATCH) { in ir_try_allocate_free_reg()
2853 IR_ASSERT(reg == IR_REG_ALL); in ir_try_allocate_free_reg()
2857 IR_REGSET_EXCL(available, reg); in ir_try_allocate_free_reg()
2875 reg = other->reg; in ir_try_allocate_free_reg()
2876 IR_ASSERT(reg >= 0); in ir_try_allocate_free_reg()
2877 if (reg >= IR_REG_SCRATCH) { in ir_try_allocate_free_reg()
2880 if (reg == IR_REG_SCRATCH) { in ir_try_allocate_free_reg()
2883 IR_ASSERT(reg == IR_REG_ALL); in ir_try_allocate_free_reg()
2887 IR_REGSET_FOREACH(regset, reg) { in ir_try_allocate_free_reg()
2888 if (next < freeUntilPos[reg]) { in ir_try_allocate_free_reg()
2889 freeUntilPos[reg] = next; in ir_try_allocate_free_reg()
2892 } else if (IR_REGSET_IN(available, reg)) { in ir_try_allocate_free_reg()
2893 IR_REGSET_INCL(overlapped, reg); in ir_try_allocate_free_reg()
2894 if (next < freeUntilPos[reg]) { in ir_try_allocate_free_reg()
2895 freeUntilPos[reg] = next; in ir_try_allocate_free_reg()
2908 reg = ir_try_allocate_preferred_reg(ctx, ival, available, freeUntilPos); in ir_try_allocate_free_reg()
2909 if (reg != IR_REG_NONE) { in ir_try_allocate_free_reg()
2910 ival->reg = reg; in ir_try_allocate_free_reg()
2916 return reg; in ir_try_allocate_free_reg()
2922 reg = ctx->live_intervals[ival->vreg]->reg; in ir_try_allocate_free_reg()
2923 if (reg >= 0 && IR_REGSET_IN(available, reg)) { in ir_try_allocate_free_reg()
2924 ival->reg = reg; in ir_try_allocate_free_reg()
2930 return reg; in ir_try_allocate_free_reg()
2944 reg = ir_get_first_reg_hint(ctx, other, non_conflicting); in ir_try_allocate_free_reg()
2946 if (reg >= 0) { in ir_try_allocate_free_reg()
2947 IR_REGSET_EXCL(non_conflicting, reg); in ir_try_allocate_free_reg()
2956 reg = IR_REGSET_FIRST(non_conflicting); in ir_try_allocate_free_reg()
2958 reg = IR_REGSET_FIRST(scratch); in ir_try_allocate_free_reg()
2961 reg = IR_REGSET_FIRST(scratch); in ir_try_allocate_free_reg()
2964 reg = IR_REGSET_FIRST(available); in ir_try_allocate_free_reg()
2966 ival->reg = reg; in ir_try_allocate_free_reg()
2972 return reg; in ir_try_allocate_free_reg()
2976 reg = IR_REG_NONE; in ir_try_allocate_free_reg()
2981 reg = i; in ir_try_allocate_free_reg()
2983 && !IR_REGSET_IN(IR_REGSET_SCRATCH, reg) in ir_try_allocate_free_reg()
2987 reg = i; in ir_try_allocate_free_reg()
3003 ival->reg = pref_reg; in ir_try_allocate_free_reg()
3005 ival->reg = reg; in ir_try_allocate_free_reg()
3008 ival->reg = reg; in ir_try_allocate_free_reg()
3017 return reg; in ir_try_allocate_free_reg()
3027 int i, reg; in ir_allocate_blocked_reg() local
3088 reg = other->reg; in ir_allocate_blocked_reg()
3089 IR_ASSERT(reg >= 0); in ir_allocate_blocked_reg()
3090 if (reg >= IR_REG_SCRATCH) { in ir_allocate_blocked_reg()
3093 if (reg == IR_REG_SCRATCH) { in ir_allocate_blocked_reg()
3096 IR_ASSERT(reg == IR_REG_ALL); in ir_allocate_blocked_reg()
3099 IR_REGSET_FOREACH(regset, reg) { in ir_allocate_blocked_reg()
3100 blockPos[reg] = nextUsePos[reg] = 0; in ir_allocate_blocked_reg()
3102 } else if (IR_REGSET_IN(available, reg)) { in ir_allocate_blocked_reg()
3104 blockPos[reg] = nextUsePos[reg] = 0; in ir_allocate_blocked_reg()
3108 if (pos < nextUsePos[reg]) { in ir_allocate_blocked_reg()
3109 nextUsePos[reg] = pos; in ir_allocate_blocked_reg()
3120 reg = other->reg; in ir_allocate_blocked_reg()
3121 IR_ASSERT(reg >= 0); in ir_allocate_blocked_reg()
3122 if (reg >= IR_REG_SCRATCH) { in ir_allocate_blocked_reg()
3128 if (reg == IR_REG_SCRATCH) { in ir_allocate_blocked_reg()
3131 IR_ASSERT(reg == IR_REG_ALL); in ir_allocate_blocked_reg()
3134 IR_REGSET_FOREACH(regset, reg) { in ir_allocate_blocked_reg()
3135 if (overlap < nextUsePos[reg]) { in ir_allocate_blocked_reg()
3136 nextUsePos[reg] = overlap; in ir_allocate_blocked_reg()
3138 if (overlap < blockPos[reg]) { in ir_allocate_blocked_reg()
3139 blockPos[reg] = overlap; in ir_allocate_blocked_reg()
3143 } else if (IR_REGSET_IN(available, reg)) { in ir_allocate_blocked_reg()
3148 if (overlap < nextUsePos[reg]) { in ir_allocate_blocked_reg()
3149 nextUsePos[reg] = overlap; in ir_allocate_blocked_reg()
3151 if (overlap < blockPos[reg]) { in ir_allocate_blocked_reg()
3152 blockPos[reg] = overlap; in ir_allocate_blocked_reg()
3157 if (pos < nextUsePos[reg]) { in ir_allocate_blocked_reg()
3158 nextUsePos[reg] = pos; in ir_allocate_blocked_reg()
3167 reg = IR_REG_NONE; in ir_allocate_blocked_reg()
3169 reg = ir_get_preferred_reg(ctx, ival, available); in ir_allocate_blocked_reg()
3171 if (reg == IR_REG_NONE) { in ir_allocate_blocked_reg()
3173 reg = IR_REGSET_FIRST(available); in ir_allocate_blocked_reg()
3177 pos = nextUsePos[reg]; in ir_allocate_blocked_reg()
3179 IR_REGSET_EXCL(tmp_regset, reg); in ir_allocate_blocked_reg()
3183 reg = i; in ir_allocate_blocked_reg()
3213 if (ival->end > blockPos[reg]) { in ir_allocate_blocked_reg()
3217 ir_live_pos split_pos = ir_last_use_pos_before(ival, blockPos[reg] + 1, in ir_allocate_blocked_reg()
3220 split_pos = ir_first_use_pos_after(ival, blockPos[reg], in ir_allocate_blocked_reg()
3227 if (split_pos >= blockPos[reg]) { in ir_allocate_blocked_reg()
3229 IR_REGSET_EXCL(available, reg); in ir_allocate_blocked_reg()
3238 split_pos = ir_find_optimal_split_position(ctx, ival, split_pos, blockPos[reg], 1); in ir_allocate_blocked_reg()
3250 if (reg == other->reg) { in ir_allocate_blocked_reg()
3292 other->reg = IR_REG_NONE; in ir_allocate_blocked_reg()
3327 if (reg == other->reg) { in ir_allocate_blocked_reg()
3347 ival->reg = reg; in ir_allocate_blocked_reg()
3354 return reg; in ir_allocate_blocked_reg()
3468 && (ival->next || ival->reg == IR_REG_NONE)) { in ir_assign_bound_spill_slots()
3490 ir_reg reg; in ir_linear_scan() local
3670 reg = ir_try_allocate_free_reg(ctx, ival, &active, inactive, &unhandled); in ir_linear_scan()
3671 if (reg == IR_REG_NONE) { in ir_linear_scan()
3672 reg = ir_allocate_blocked_reg(ctx, ival, &active, &inactive, &unhandled); in ir_linear_scan()
3701 && (ival->next || ival->reg == IR_REG_NONE) in ir_linear_scan()
3853 static void ir_set_fused_reg(ir_ctx *ctx, ir_ref root, ir_ref ref_and_op, int8_t reg) in ir_set_fused_reg() argument
3857 IR_ASSERT(reg != IR_REG_NONE); in ir_set_fused_reg()
3864 ir_strtab_lookup(ctx->fused_regs, key, 8, 0x10000000 | reg); in ir_set_fused_reg()
3872 int8_t reg, old_reg; in assign_regs() local
3886 if (ival->reg != IR_REG_NONE) { in assign_regs()
3887 reg = ival->reg; in assign_regs()
3888 IR_REGSET_INCL(used_regs, reg); in assign_regs()
3892 ir_set_alocated_reg(ctx, ref, use_pos->op_num, reg); in assign_regs()
3908 if (ival->reg != IR_REG_NONE) { in assign_regs()
3909 IR_REGSET_INCL(used_regs, ival->reg); in assign_regs()
3912 reg = ival->reg; in assign_regs()
3917 ir_set_alocated_reg(ctx, ref, use_pos->op_num, reg); in assign_regs()
3926 if (ival->reg != IR_REG_NONE) { in assign_regs()
3930 IR_REGSET_INCL(used_regs, ival->reg); in assign_regs()
3933 reg = ival->reg; in assign_regs()
3943 ir_set_alocated_reg(ctx, ref, use_pos->op_num, reg); in assign_regs()
3951 reg = IR_REG_NONE; in assign_regs()
3956 reg = IR_REG_NONE; in assign_regs()
3964 reg |= IR_REG_SPILL_SPECIAL; in assign_regs()
3966 reg |= IR_REG_SPILL_STORE; in assign_regs()
3973 && use_pos->hint != reg in assign_regs()
3979 reg = IR_REG_NONE; in assign_regs()
3988 ir_set_alocated_reg(ctx, ref, use_pos->op_num, reg); in assign_regs()
3993 reg |= IR_REG_SPILL_SPECIAL; in assign_regs()
3995 reg |= IR_REG_SPILL_LOAD; in assign_regs()
4009 reg |= IR_REG_SPILL_SPECIAL; in assign_regs()
4011 reg |= IR_REG_SPILL_LOAD; in assign_regs()
4013 if (reg != old_reg) { in assign_regs()
4016 ir_set_fused_reg(ctx, ref, -use_pos->hint_ref * sizeof(ir_ref) + use_pos->op_num, reg); in assign_regs()
4027 reg = IR_REG_NONE; in assign_regs()
4031 if (reg != old_reg) { in assign_regs()
4034 ir_set_fused_reg(ctx, ref, -use_pos->hint_ref * sizeof(ir_ref) + use_pos->op_num, reg); in assign_regs()
4044 ir_set_alocated_reg(ctx, ref, use_pos->op_num, reg); in assign_regs()
4055 reg = IR_REG_SPILL_STORE | IR_REG_STACK_POINTER; in assign_regs()
4056 ir_set_alocated_reg(ctx, ref, use_pos->op_num, reg); in assign_regs()
4073 IR_ASSERT(ival->reg != IR_REG_NONE); in assign_regs()
4074 IR_REGSET_INCL(used_regs, ival->reg); in assign_regs()
4075 reg = ival->reg; in assign_regs()
4083 reg |= IR_REG_SPILL_LOAD; in assign_regs()
4087 reg |= IR_REG_SPILL_LOAD; in assign_regs()
4091 ir_set_alocated_reg(ctx, ival->tmp_ref, ival->tmp_op_num, reg); in assign_regs()
