Lines Matching refs:reg
189 |.macro ASM_REG_IMM_OP, op, type, reg, val
191 | op Rx(reg), #val
193 | op Rw(reg), #val
197 |.macro ASM_FP_REG_IMM_OP, op, type, reg, val
199 | op Rd(reg-IR_REG_FP_FIRST), #val
202 | op Rs(reg-IR_REG_FP_FIRST), #val
265 const char *ir_reg_name(int8_t reg, ir_type type)
267 if (reg >= IR_REG_NUM) {
268 if (reg == IR_REG_SCRATCH) {
271 IR_ASSERT(reg == IR_REG_ALL);
275 IR_ASSERT(reg >= 0 && reg < IR_REG_NUM);
277 type = (reg < IR_REG_FP_FIRST) ? IR_ADDR : IR_DOUBLE;
280 return _ir_reg_name[reg];
282 return _ir_reg_name32[reg];
1112 static int32_t ir_ref_spill_slot_offset(ir_ctx *ctx, ir_ref ref, ir_reg *reg)
1121 *reg = ctx->spill_base;
1124 *reg = (ctx->flags & IR_USE_FRAME_POINTER) ? IR_REG_FRAME_POINTER : IR_REG_STACK_POINTER;
1156 static int32_t ir_var_spill_slot(ir_ctx *ctx, ir_ref ref, ir_reg *reg)
1161 *reg = (ctx->flags & IR_USE_FRAME_POINTER) ? IR_REG_FRAME_POINTER : IR_REG_STACK_POINTER;
1184 static void ir_emit_load_imm_int(ir_ctx *ctx, ir_type type, ir_reg reg, int64_t val)
1192 if (reg != IR_REG_ZR) {
1193 | mov Rx(reg), xzr
1196 | movz Rx(reg), #((uint64_t)(val))
1198 | movn Rx(reg), #(~((uint64_t)(val)))
1200 | movz Rx(reg), #((uint64_t)(val) & 0xffff)
1202 | movk Rx(reg), #(((uint64_t)(val) >> 16) & 0xffff), lsl #16
1205 | movk Rx(reg), #(((uint64_t)(val) >> 32) & 0xffff), lsl #32
1208 | movk Rx(reg), #(((uint64_t)(val) >> 48) & 0xffff), lsl #48
1211 | movz Rx(reg), #(((uint64_t)(val) >> 16) & 0xffff), lsl #16
1213 | movk Rx(reg), #(((uint64_t)(val) >> 32) & 0xffff), lsl #32
1216 | movk Rx(reg), #(((uint64_t)(val) >> 48) & 0xffff), lsl #48
1219 | movz Rx(reg), #(((uint64_t)(val) >> 32) & 0xffff), lsl #32
1221 | movk Rx(reg), #(((uint64_t)(val) >> 48) & 0xffff), lsl #48
1224 | movz Rx(reg), #(((uint64_t)(val) >> 48) & 0xffff), lsl #48
1228 if (reg != IR_REG_ZR) {
1229 | mov Rw(reg), wzr
1232 | movz Rw(reg), #((uint64_t)(val))
1234 | movn Rw(reg), #(~((uint64_t)(val)))
1236 | movz Rw(reg), #((uint64_t)(val) & 0xffff)
1238 | movk Rw(reg), #(((uint64_t)(val) >> 16) & 0xffff), lsl #16
1241 | movz Rw(reg), #(((uint64_t)(val) >> 16) & 0xffff), lsl #16
1246 static void ir_emit_load_mem_int(ir_ctx *ctx, ir_type type, ir_reg reg, ir_mem mem)
1260 | ldr Rx(reg), [Rx(base_reg), #offset]
1263 | ldr Rw(reg), [Rx(base_reg), #offset]
1267 | ldrsh Rw(reg), [Rx(base_reg), #offset]
1269 | ldrh Rw(reg), [Rx(base_reg), #offset]
1274 | ldrsb Rw(reg), [Rx(base_reg), #offset]
1276 | ldrb Rw(reg), [Rx(base_reg), #offset]
1294 | ldr Rx(reg), [Rx(base_reg), Rx(index_reg)]
1297 | ldr Rw(reg), [Rx(base_reg), Rx(index_reg)]
1301 | ldrsh Rw(reg), [Rx(base_reg), Rx(index_reg)]
1303 | ldrh Rw(reg), [Rx(base_reg), Rx(index_reg)]
1308 | ldrsb Rw(reg), [Rx(base_reg), Rx(index_reg)]
1310 | ldrb Rw(reg), [Rx(base_reg), Rx(index_reg)]
1316 static void ir_emit_load_imm_fp(ir_ctx *ctx, ir_type type, ir_reg reg, ir_ref src)
1324 | fmov Rs(reg-IR_REG_FP_FIRST), wzr
1326 | fmov Rd(reg-IR_REG_FP_FIRST), xzr
1330 | ldr Rd(reg-IR_REG_FP_FIRST), =>label
1333 | ldr Rs(reg-IR_REG_FP_FIRST), =>label
1338 static void ir_emit_load_mem_fp(ir_ctx *ctx, ir_type type, ir_reg reg, ir_mem mem)
1349 | ldr Rd(reg-IR_REG_FP_FIRST), [Rx(base_reg), #offset]
1352 | ldr Rs(reg-IR_REG_FP_FIRST), [Rx(base_reg), #offset]
1365 | ldr Rd(reg-IR_REG_FP_FIRST), [Rx(base_reg), Rx(index_reg)]
1368 | ldr Rs(reg-IR_REG_FP_FIRST), [Rx(base_reg), Rx(index_reg)]
1372 static void ir_emit_load_mem(ir_ctx *ctx, ir_type type, ir_reg reg, ir_mem mem)
1375 ir_emit_load_mem_int(ctx, type, reg, mem);
1377 ir_emit_load_mem_fp(ctx, type, reg, mem);
1381 static void ir_load_local_addr(ir_ctx *ctx, ir_reg reg, ir_ref src)
1390 | add Rx(reg), Rx(base), #offset
1398 static void ir_emit_load(ir_ctx *ctx, ir_type type, ir_reg reg, ir_ref src)
1407 ir_emit_load_imm_int(ctx, type, reg, (intptr_t)addr);
1413 | adr Rx(reg), =>label
1415 ir_emit_load_imm_int(ctx, type, reg, insn->val.i64);
1418 ir_emit_load_imm_fp(ctx, type, reg, src);
1422 ir_emit_load_mem(ctx, type, reg, mem);
1424 ir_load_local_addr(ctx, reg, src);
1428 static void ir_emit_store_mem_int(ir_ctx *ctx, ir_type type, ir_mem mem, ir_reg reg)
1442 | str Rx(reg), [Rx(base_reg), #offset]
1445 | str Rw(reg), [Rx(base_reg), #offset]
1448 | strh Rw(reg), [Rx(base_reg), #offset]
1451 | strb Rw(reg), [Rx(base_reg), #offset]
1468 | str Rx(reg), [Rx(base_reg), Rx(index_reg)]
1471 | str Rw(reg), [Rx(base_reg), Rx(index_reg)]
1474 | strh Rw(reg), [Rx(base_reg), Rx(index_reg)]
1477 | strb Rw(reg), [Rx(base_reg), Rx(index_reg)]
1482 static void ir_emit_store_mem_fp(ir_ctx *ctx, ir_type type, ir_mem mem, ir_reg reg)
1493 | str Rd(reg-IR_REG_FP_FIRST), [Rx(base_reg), #offset]
1496 | str Rs(reg-IR_REG_FP_FIRST), [Rx(base_reg), #offset]
1509 | str Rd(reg-IR_REG_FP_FIRST), [Rx(base_reg), Rx(index_reg)]
1512 | str Rs(reg-IR_REG_FP_FIRST), [Rx(base_reg), Rx(index_reg)]
1516 static void ir_emit_store_mem(ir_ctx *ctx, ir_type type, ir_mem mem, ir_reg reg)
1519 ir_emit_store_mem_int(ctx, type, mem, reg);
1521 ir_emit_store_mem_fp(ctx, type, mem, reg);
1525 static void ir_emit_store(ir_ctx *ctx, ir_type type, ir_ref dst, ir_reg reg)
1528 ir_emit_store_mem(ctx, type, ir_ref_spill_slot(ctx, dst), reg);
2077 ir_reg reg;
2080 reg = insn->op3;
2091 | ASM_REG_REG_IMM_OP add, type, reg, reg, val->i32
2094 | ASM_REG_REG_IMM_OP sub, type, reg, reg, val->i32
2097 | ASM_REG_REG_IMM_OP orr, type, reg, reg, val->i32
2100 | ASM_REG_REG_IMM_OP and, type, reg, reg, val->i32
2103 | ASM_REG_REG_IMM_OP eor, type, reg, reg, val->i32
2115 | ASM_REG_REG_REG_OP add, type, reg, reg, op2_reg
2118 | ASM_REG_REG_REG_OP sub, type, reg, reg, op2_reg
2121 | ASM_REG_REG_REG_OP mul, type, reg, reg, op2_reg
2124 | ASM_REG_REG_REG_OP orr, type, reg, reg, op2_reg
2127 | ASM_REG_REG_REG_OP and, type, reg, reg, op2_reg
2130 | ASM_REG_REG_REG_OP eor, type, reg, reg, op2_reg
2926 …void ir_emit_jz(ir_ctx *ctx, uint32_t b, uint32_t next_block, uint8_t op, ir_type type, ir_reg reg)
2944 | cbz Rx(reg), =>true_block
2946 | cbz Rw(reg), =>true_block
2951 | cbnz Rx(reg), =>true_block
2953 | cbnz Rw(reg), =>true_block
3668 /* same reg */
3695 /* same reg */
3785 ir_reg reg;
3792 reg = (ctx->flags & IR_USE_FRAME_POINTER) ? IR_REG_FRAME_POINTER : IR_REG_STACK_POINTER;
3795 return IR_MEM_BO(reg, offset);
3798 reg = ir_get_fused_reg(ctx, root, ref * sizeof(ir_ref) + 1);
3800 reg = ctx->regs[ref][1];
3802 if (IR_REG_SPILLED(reg)) {
3803 reg = IR_REG_NUM(reg);
3804 ir_emit_load(ctx, IR_ADDR, reg, addr_insn->op1);
3806 return IR_MEM_BO(reg, ctx->ir_base[addr_insn->op2].val.i32);
3810 reg = (ctx->flags & IR_USE_FRAME_POINTER) ? IR_REG_FRAME_POINTER : IR_REG_STACK_POINTER;
3812 return IR_MEM_BO(reg, offset);
5035 static void ir_emit_guard_jz(ir_ctx *ctx, uint8_t op, void *addr, ir_type type, ir_reg reg)
5042 | cbnz Rx(reg), &addr
5044 | cbnz Rw(reg), &addr
5049 | cbz Rx(reg), &addr
5051 | cbz Rw(reg), &addr
5236 ir_reg reg = IR_REG_NUM(ctx->regs[def][0]);
5244 || code = 0xd53bd060 | reg; // TODO: hard-coded: mrs reg, tpidrro_el0
5246 | and Rx(reg), Rx(reg), #0xfffffffffffffff8
5247 |//??? MEM_ACCESS_64_WITH_UOFFSET_64 ldr, Rx(reg), Rx(reg), #insn->op2, TMP1
5248 |//??? MEM_ACCESS_64_WITH_UOFFSET_64 ldr, Rx(reg), Rx(reg), #insn->op3, TMP1
5250 || code = 0xd53bd040 | reg; // TODO: hard-coded: mrs reg, tpidr_el0
5254 | ldr Rx(reg), [Rx(reg), #insn->op2]
5256 | ldr Rx(reg), [Rx(reg), #0]
5257 | ldr Rx(reg), [Rx(reg), #insn->op2]
5258 | ldr Rx(reg), [Rx(reg), #insn->op3]
5262 | ldr Rx(reg), [Rx(reg), #insn->op2]
5264 | ldr Rx(reg), [Rx(reg), #-8]
5265 | ldr Rx(reg), [Rx(reg), #insn->op2]
5266 | ldr Rx(reg), [Rx(reg), #insn->op3]
5270 | ldr Rx(reg), [Rx(reg), #insn->op2]
5274 ir_emit_store(ctx, IR_ADDR, def, reg);
5533 && (ival->next || ival->reg == IR_REG_NONE)) {
5564 ir_reg reg;
5601 reg = constraints.def_reg;
5602 if (reg != IR_REG_NONE && IR_REGSET_IN(available, reg)) {
5603 IR_REGSET_EXCL(available, reg);
5604 ctx->regs[i][0] = reg | IR_REG_SPILL_STORE;
5612 reg = ir_get_free_reg(insn->type, available);
5613 IR_REGSET_EXCL(available, reg);
5614 ctx->regs[i][0] = reg | IR_REG_SPILL_STORE;
5622 ival->reg = IR_REG_NONE;
5625 if (insn->op == IR_PARAM && reg == IR_REG_NONE) {
5653 ival->reg = IR_REG_NONE;
5665 ival->reg = IR_REG_NONE;
5680 ir_reg reg = ir_get_free_reg(constraints.tmp_regs[n].type, available);
5682 IR_REGSET_EXCL(available, reg);
5686 reg |= IR_REG_SPILL_LOAD;
5688 ctx->regs[i][constraints.tmp_regs[n].num] = reg;
5689 } else if (constraints.tmp_regs[n].reg == IR_REG_SCRATCH) {
5692 IR_REGSET_EXCL(available, constraints.tmp_regs[n].reg);
5701 ir_reg reg = IR_REG_NUM(ctx->regs[i][0]);
5702 ctx->regs[i][1] = reg | IR_REG_SPILL_LOAD;
5705 ir_reg reg = (j < constraints.hints_count) ? constraints.hints[j] : IR_REG_NONE;
5707 if (reg != IR_REG_NONE && IR_REGSET_IN(available, reg)) {
5708 IR_REGSET_EXCL(available, reg);
5709 ctx->regs[i][j] = reg | IR_REG_SPILL_LOAD;
5713 reg = ir_get_free_reg(ctx->ir_base[input].type, available);
5714 IR_REGSET_EXCL(available, reg);
5715 ctx->regs[i][j] = reg | IR_REG_SPILL_LOAD;
5769 ir_reg reg;
5770 (void) reg;
5772 IR_REGSET_FOREACH(used_preserved_regs, reg) {
