Lines Matching refs:v0
99 ($zero,$at,$v0,$v1)=map("\$$_",(0..3));
143 move $v0,$zero
145 move $a0,$v0
178 $ADDU $t1,$v0
179 sltu $v0,$t1,$v0 # All manuals say it "compares 32-bit
185 $ADDU $v0,$t0
189 $ADDU $v0,$at
193 $ADDU $t3,$v0
194 sltu $v0,$t3,$v0
198 $ADDU $v0,$t2
202 $ADDU $v0,$at
207 $ADDU $ta1,$v0
208 sltu $v0,$ta1,$v0
212 $ADDU $v0,$ta0
216 $ADDU $v0,$at
220 $ADDU $ta3,$v0
221 sltu $v0,$ta3,$v0
225 $ADDU $v0,$ta2
230 $ADDU $v0,$at
241 $ADDU $t1,$v0
242 sltu $v0,$t1,$v0
246 $ADDU $v0,$t0
249 $ADDU $v0,$at
256 $ADDU $t1,$v0
257 sltu $v0,$t1,$v0
261 $ADDU $v0,$t0
264 $ADDU $v0,$at
270 $ADDU $t1,$v0
271 sltu $v0,$t1,$v0
275 $ADDU $v0,$t0
278 $ADDU $v0,$at
293 move $a0,$v0
302 move $v0,$zero
304 move $a0,$v0
337 $ADDU $v0,$at
338 sltu $t1,$v0,$at
340 $ST $v0,0($a0)
341 $ADDU $v0,$t1,$t0
348 $ADDU $v0,$at
349 sltu $t3,$v0,$at
351 $ST $v0,-3*$BNSZ($a0)
352 $ADDU $v0,$t3,$t2
356 $ADDU $v0,$at
357 sltu $ta1,$v0,$at
359 $ST $v0,-2*$BNSZ($a0)
360 $ADDU $v0,$ta1,$ta0
365 $ADDU $v0,$at
366 sltu $ta3,$v0,$at
367 $ST $v0,-$BNSZ($a0)
370 $ADDU $v0,$ta3,$ta2
382 $ADDU $v0,$at
383 sltu $t1,$v0,$at
384 $ST $v0,0($a0)
385 $ADDU $v0,$t1,$t0
393 $ADDU $v0,$at
394 sltu $t1,$v0,$at
395 $ST $v0,$BNSZ($a0)
396 $ADDU $v0,$t1,$t0
403 $ADDU $v0,$at
404 sltu $t1,$v0,$at
405 $ST $v0,2*$BNSZ($a0)
406 $ADDU $v0,$t1,$t0
421 move $a0,$v0
430 move $v0,$zero
432 move $a0,$v0
537 move $a0,$v0
547 move $v0,$zero
549 move $a0,$v0
590 $ADDU $t0,$ta0,$v0
591 sltu $v0,$t0,$ta0
593 $ADDU $v0,$t8
597 $ADDU $t1,$ta1,$v0
598 sltu $v0,$t1,$ta1
600 $ADDU $v0,$t9
604 $ADDU $t2,$ta2,$v0
605 sltu $v0,$t2,$ta2
607 $ADDU $v0,$t8
611 $ADDU $t3,$ta3,$v0
612 sltu $v0,$t3,$ta3
617 $ADDU $v0,$t9
629 $ADDU $t0,$ta0,$v0
630 sltu $v0,$t0,$ta0
632 $ADDU $v0,$t8
640 $ADDU $t1,$ta1,$v0
641 sltu $v0,$t1,$ta1
643 $ADDU $v0,$t9
650 $ADDU $t2,$ta2,$v0
651 sltu $v0,$t2,$ta2
653 $ADDU $v0,$t8
668 move $a0,$v0
678 move $v0,$zero
721 $SUBU $t0,$ta0,$v0
722 sgtu $v0,$t0,$ta0
724 $ADDU $v0,$t8
728 $SUBU $t1,$ta1,$v0
729 sgtu $v0,$t1,$ta1
731 $ADDU $v0,$t9
736 $SUBU $t2,$ta2,$v0
737 sgtu $v0,$t2,$ta2
739 $ADDU $v0,$t8
743 $SUBU $t3,$ta3,$v0
744 sgtu $v0,$t3,$ta3
749 $ADDU $v0,$t9
761 $SUBU $t0,$ta0,$v0
762 sgtu $v0,$t0,$ta0
764 $ADDU $v0,$t8
772 $SUBU $t1,$ta1,$v0
773 sgtu $v0,$t1,$ta1
775 $ADDU $v0,$t9
782 $SUBU $t2,$ta2,$v0
783 sgtu $v0,$t2,$ta2
785 $ADDU $v0,$t8
800 move $a0,$v0
823 li $v0,-1
825 move $a0,$v0
849 $MULTU ($ta2,$v0)
852 mfhi ($t1,$ta2,$v0)
853 mflo ($t0,$ta2,$v0)
869 $SUBU $v0,1
870 $ADDU $v0,1
885 move $a0,$v0
895 li $v0,-1 # I would rather signal div-by-zero
898 move $a0,$v0
971 sltu $v0,$t0,$a2
975 $SUBU $t1,$v0
984 $SLL $v0,$QT,4*$BNSZ # bits
1016 or $v0,$QT
1033 move $a0,$v0
1044 ($t_1,$t_2,$c_1,$c_2,$c_3)=($t8,$t9,$v0,$v1,$a3);
