Lines Matching refs:op2
113 |.macro ASM_EXPAND_OP1_MEM, MACRO, op, type, op1, op2
121 | MACRO op, type, [offset], op2
123 | MACRO op, type, [Ra(base)+offset], op2
127 | MACRO op, type, [Ra(index)*8+offset], op2
129 | MACRO op, type, [Ra(base)+Ra(index)*8+offset], op2
133 | MACRO op, type, [Ra(index)*4+offset], op2
135 | MACRO op, type, [Ra(base)+Ra(index)*4+offset], op2
139 | MACRO op, type, [Ra(index)*2+offset], op2
141 | MACRO op, type, [Ra(base)+Ra(index)*2+offset], op2
146 | MACRO op, type, [Ra(index)+offset], op2
148 | MACRO op, type, [Ra(base)+Ra(index)+offset], op2
154 |.macro ASM_EXPAND_OP2_MEM, MACRO, op, type, op1, op2
156 || int32_t offset = IR_MEM_OFFSET(op2);
157 || int32_t base = IR_MEM_BASE(op2);
158 || int32_t index = IR_MEM_INDEX(op2);
159 || int32_t scale = IR_MEM_SCALE(op2);
195 |.macro ASM_EXPAND_OP2_MEM_3, MACRO, op, type, op1, op2, op3
197 || int32_t offset = IR_MEM_OFFSET(op2);
198 || int32_t base = IR_MEM_BASE(op2);
199 || int32_t index = IR_MEM_INDEX(op2);
200 || int32_t scale = IR_MEM_SCALE(op2);
236 |.macro ASM_EXPAND_OP3_MEM, MACRO, op, type, op1, op2, op3
244 | MACRO op, type, op1, op2, [offset]
246 | MACRO op, type, op1, op2, [Ra(base)+offset]
250 | MACRO op, type, op1, op2, [Ra(index)*8+offset]
252 | MACRO op, type, op1, op2, [Ra(base)+Ra(index)*8+offset]
256 | MACRO op, type, op1, op2, [Ra(index)*4+offset]
258 | MACRO op, type, op1, op2, [Ra(base)+Ra(index)*4+offset]
262 | MACRO op, type, op1, op2, [Ra(index)*2+offset]
264 | MACRO op, type, op1, op2, [Ra(base)+Ra(index)*2+offset]
269 | MACRO op, type, op1, op2, [Ra(index)+offset]
271 | MACRO op, type, op1, op2, [Ra(base)+Ra(index)+offset]
298 |.macro ASM_EXPAND_TYPE_MEM_REG, op, type, op1, op2
303 | op byte op1, Rb(op2)
306 | op word op1, Rw(op2)
309 | op dword op1, Rd(op2)
313 | op qword op1, Rq(op2)
319 |.macro ASM_EXPAND_TYPE_MEM_TXT, op, type, op1, op2
324 | op byte op1, op2
327 | op word op1, op2
330 | op dword op1, op2
334 | op qword op1, op2
340 |.macro ASM_EXPAND_TYPE_MEM_IMM, op, type, op1, op2
345 | op byte op1, (op2 & 0xff)
348 | op word op1, (op2 & 0xffff)
351 | op dword op1, op2
355 | op qword op1, op2
361 |.macro ASM_EXPAND_TYPE_REG_MEM, op, type, op1, op2
366 | op Rb(op1), byte op2
369 | op Rw(op1), word op2
372 | op Rd(op1), dword op2
376 | op Rq(op1), qword op2
423 |.macro ASM_TXT_TMEM_OP, op, op1, type, op2
425 || int32_t offset = IR_MEM_OFFSET(op2);
426 || int32_t base = IR_MEM_BASE(op2);
427 || int32_t index = IR_MEM_INDEX(op2);
428 || int32_t scale = IR_MEM_SCALE(op2);
464 |.macro ASM_TMEM_TXT_OP, op, type, op1, op2
472 | op type [offset], op2
474 | op type [Ra(base)+offset], op2
478 | op type [Ra(index)*8+offset], op2
480 | op type [Ra(base)+Ra(index)*8+offset], op2
484 | op type [Ra(index)*4+offset], op2
486 | op type [Ra(base)+Ra(index)*4+offset], op2
490 | op type [Ra(index)*2+offset], op2
492 | op type [Ra(base)+Ra(index)*2+offset], op2
497 | op type [Ra(index)+offset], op2
499 | op type [Ra(base)+Ra(index)+offset], op2
505 |.macro ASM_TXT_TXT_TMEM_OP, op, op1, op2, type, op3
513 | op op1, op2, type [offset]
515 | op op1, op2, type [Ra(base)+offset]
519 | op op1, op2, type [Ra(index)*8+offset]
521 | op op1, op2, type [Ra(base)+Ra(index)*8+offset]
525 | op op1, op2, type [Ra(index)*4+offset]
527 | op op1, op2, type [Ra(base)+Ra(index)*4+offset]
531 | op op1, op2, type [Ra(index)*2+offset]
533 | op op1, op2, type [Ra(base)+Ra(index)*2+offset]
538 | op op1, op2, type [Ra(index)+offset]
540 | op op1, op2, type [Ra(base)+Ra(index)+offset]
571 |.macro ASM_REG_REG_OP, op, type, op1, op2
576 | op Rb(op1), Rb(op2)
579 | op Rw(op1), Rw(op2)
582 | op Rd(op1), Rd(op2)
586 | op Rq(op1), Rq(op2)
592 |.macro ASM_REG_REG_OP2, op, type, op1, op2
598 | op Rw(op1), Rw(op2)
601 | op Rd(op1), Rd(op2)
605 | op Rq(op1), Rq(op2)
611 |.macro ASM_REG_TXT_OP, op, type, op1, op2
616 | op Rb(op1), op2
619 | op Rw(op1), op2
622 | op Rd(op1), op2
626 | op Rq(op1), op2
632 |.macro ASM_REG_IMM_OP, op, type, op1, op2
637 | op Rb(op1), (op2 & 0xff)
640 | op Rw(op1), (op2 & 0xffff)
643 | op Rd(op1), op2
647 | op Rq(op1), op2
653 |.macro ASM_MEM_REG_OP, op, type, op1, op2
654 | ASM_EXPAND_OP1_MEM ASM_EXPAND_TYPE_MEM_REG, op, type, op1, op2
657 |.macro ASM_MEM_TXT_OP, op, type, op1, op2
658 | ASM_EXPAND_OP1_MEM ASM_EXPAND_TYPE_MEM_TXT, op, type, op1, op2
661 |.macro ASM_MEM_IMM_OP, op, type, op1, op2
662 | ASM_EXPAND_OP1_MEM ASM_EXPAND_TYPE_MEM_IMM, op, type, op1, op2
665 |.macro ASM_REG_MEM_OP, op, type, op1, op2
666 | ASM_EXPAND_OP2_MEM ASM_REG_TXT_OP, op, type, op1, op2
669 |.macro ASM_REG_REG_MUL, op, type, op1, op2
674 | op Rw(op1), Rw(op2)
677 | op Rd(op1), Rd(op2)
681 | op Rq(op1), Rq(op2)
687 |.macro ASM_REG_IMM_MUL, op, type, op1, op2
692 | op Rw(op1), op2
695 | op Rd(op1), op2
699 | op Rq(op1), op2
705 |.macro ASM_REG_TXT_MUL, op, type, op1, op2
710 | op Rw(op1), op2
713 | op Rd(op1), op2
717 | op Rq(op1), op2
723 |.macro ASM_REG_MEM_MUL, op, type, op1, op2
724 | ASM_EXPAND_OP2_MEM ASM_REG_TXT_MUL, op, type, op1, op2
727 |.macro ASM_REG_TXT_TXT_MUL, op, type, op1, op2, op3
732 | op Rw(op1), op2, op3
735 | op Rd(op1), op2, op3
739 | op Rq(op1), op2, op3
745 |.macro ASM_REG_MEM_TXT_MUL, op, type, op1, op2, op3
746 | ASM_EXPAND_OP2_MEM_3 ASM_REG_TXT_TXT_MUL, imul, type, op1, op2, op3
749 |.macro ASM_SSE2_REG_REG_OP, op, type, op1, op2
751 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST)
754 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST)
758 |.macro ASM_SSE2_REG_TXT_OP, op, type, op1, op2
760 | op..d xmm(op1-IR_REG_FP_FIRST), qword op2
763 | op..s xmm(op1-IR_REG_FP_FIRST), dword op2
767 |.macro ASM_SSE2_REG_MEM_OP, op, type, op1, op2
768 | ASM_EXPAND_OP2_MEM ASM_SSE2_REG_TXT_OP, op, type, op1, op2
771 |.macro ASM_AVX_REG_REG_REG_OP, op, type, op1, op2, op3
773 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), xmm(op3-IR_REG_FP_FIRST)
776 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), xmm(op3-IR_REG_FP_FIRST)
780 |.macro ASM_AVX_REG_REG_TXT_OP, op, type, op1, op2, op3
782 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), qword op3
785 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), dword op3
789 |.macro ASM_AVX_REG_REG_MEM_OP, op, type, op1, op2, op3
790 | ASM_EXPAND_OP3_MEM ASM_AVX_REG_REG_TXT_OP, op, type, op1, op2, op3
793 |.macro ASM_FP_REG_REG_OP, op, type, op1, op2
795 | ASM_SSE2_REG_REG_OP v..op, type, op1, op2
797 | ASM_SSE2_REG_REG_OP op, type, op1, op2
818 |.macro ASM_FP_MEM_REG_OP, op, type, op1, op2
819 | ASM_EXPAND_OP1_MEM ASM_FP_TXT_REG_OP, op, type, op1, op2
822 |.macro ASM_FP_REG_TXT_OP, op, type, op1, op2
824 | ASM_SSE2_REG_TXT_OP v..op, type, op1, op2
826 | ASM_SSE2_REG_TXT_OP op, type, op1, op2
830 |.macro ASM_FP_REG_MEM_OP, op, type, op1, op2
832 | ASM_SSE2_REG_MEM_OP v..op, type, op1, op2
834 | ASM_SSE2_REG_MEM_OP op, type, op1, op2
838 |.macro ASM_SSE2_REG_REG_TXT_OP, op, type, op1, op2, op3
840 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), op3
843 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), op3
847 |.macro ASM_SSE2_REG_REG_REG_TXT_OP, op, type, op1, op2, op3, op4
849 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), xmm(op3-IR_REG_FP_FIRST), op4
852 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), xmm(op3-IR_REG_FP_FIRST), op4
856 |.macro ASM_FP_REG_REG_TXT_OP, op, type, op1, op2, op3
858 | ASM_SSE2_REG_REG_REG_TXT_OP v..op, type, op1, op2, op3
860 | ASM_SSE2_REG_REG_TXT_OP op, type, op1, op2, op3
1154 if (IR_IS_CONST_REF(insn->op2)) {
1155 if (insn->op1 != insn->op2) {
1156 n = ir_add_const_tmp_reg(ctx, insn->op2, 2, n, constraints);
1158 } else if (ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA) {
1211 if (IR_IS_CONST_REF(insn->op2) && insn->op1 != insn->op2) {
1230 if (IR_IS_CONST_REF(insn->op2)) {
1231 if (insn->op1 != insn->op2) {
1233 n = ir_add_const_tmp_reg(ctx, insn->op2, 2, n, constraints);
1235 } else if (ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA) {
1275 } else if (IR_IS_CONST_REF(insn->op2) || ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA) {
1302 if (IR_IS_CONST_REF(insn->op2)) {
1303 n = ir_add_const_tmp_reg(ctx, insn->op2, 2, n, constraints);
1335 if (IR_IS_CONST_REF(insn->op2)) {
1336 n = ir_add_const_tmp_reg(ctx, insn->op2, 2, n, constraints);
1342 if (IR_IS_CONST_REF(insn->op2)) {
1343 n = ir_add_const_tmp_reg(ctx, insn->op2, 2, n, constraints);
1354 if (IR_IS_CONST_REF(insn->op2)) {
1355 insn = &ctx->ir_base[insn->op2];
1380 if (!IR_IS_CONST_REF(insn->op2)) {
1403 int64_t offset = ctx->ir_base[insn->op2].val.u64 - 1;
1414 int64_t offset = ctx->ir_base[insn->op2].val.u64 - 1;
1427 int64_t offset = ctx->ir_base[insn->op2].val.u64 - 1;
1496 constraints->def_reg = ctx->ir_base[ref].op2;
1556 SWAP_REFS(insn->op1, insn->op2);
1564 if (insn->op1 == insn->op2) {
1566 } else if (ir_match_try_fuse_load(ctx, insn->op2, ref)) {
1619 if (IR_IS_CONST_REF(insn->op2)) {
1620 op2_insn = &ctx->ir_base[insn->op2];
1628 } else if (insn->op2 != ref) {
1631 } else if (insn->op2 == ref && insn->op1 != insn->op2) {
1651 && IR_IS_CONST_REF(insn->op2)) {
1652 insn = &ctx->ir_base[insn->op2];
1703 ir_ref addr_ref = ctx->ir_base[ref].op2;
1728 ir_ref addr_ref = ctx->ir_base[ref].op2;
1755 if (IR_IS_CONST_REF(insn->op2)
1756 && ir_may_fuse_imm(ctx, &ctx->ir_base[insn->op2])) {
1758 } else if (ir_match_try_fuse_load(ctx, insn->op2, root)) {
1767 if (!IR_IS_CONST_REF(insn->op2)
1768 && !ir_match_try_fuse_load(ctx, insn->op2, root)
1776 if (IR_IS_CONST_REF(insn->op2)
1777 && ir_may_fuse_imm(ctx, &ctx->ir_base[insn->op2])) {
1779 } else if (!ir_match_try_fuse_load(ctx, insn->op2, root)
1790 if (IR_IS_CONST_REF(insn->op2)
1791 && ir_may_fuse_imm(ctx, &ctx->ir_base[insn->op2])) {
1793 } else if (!ir_match_try_fuse_load(ctx, insn->op2, root)
1807 ir_match_fuse_load(ctx, insn->op2, root);
1808 } else if (IR_IS_CONST_REF(insn->op2) && !IR_IS_FP_ZERO(ctx->ir_base[insn->op2])) {
1810 } else if (ir_match_try_fuse_load(ctx, insn->op2, root)) {
1835 if (IR_IS_CONST_REF(insn->op2) && !IR_IS_FP_ZERO(ctx->ir_base[insn->op2])) {
1837 } else if (ir_match_try_fuse_load(ctx, insn->op2, root)) {
1934 if (IR_IS_CONST_REF(insn->op2)
1935 && !IR_IS_SYM_CONST(ctx->ir_base[insn->op2].op)
1936 && ctx->ir_base[insn->op2].val.i64 == 0
1955 ir_match_fuse_load(ctx, op1_insn->op2, ref);
1971 if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
1972 op2_insn = &ctx->ir_base[insn->op2];
2034 if (insn->op1 != insn->op2) {
2042 if (ctx->use_lists[insn->op2].count == 1 || ir_match_fuse_addr_all_useges(ctx, insn->op2)) {
2043 rule = ctx->rules[insn->op2];
2045 ctx->rules[insn->op2] = rule = ir_match_insn(ctx, insn->op2);
2049 ctx->rules[insn->op2] = IR_FUSED | IR_SIMPLE | IR_LEA_SI;
2057 if (ctx->use_lists[insn->op2].count == 1) {
2058 rule = ctx->rules[insn->op2];
2060 ctx->rules[insn->op2] = rule = ir_match_insn(ctx, insn->op2);
2064 ctx->rules[insn->op2] = IR_FUSED | IR_SIMPLE | IR_LEA_OB;
2072 if (ctx->use_lists[insn->op2].count == 1 || ir_match_fuse_addr_all_useges(ctx, insn->op2)) {
2073 uint32_t rule = ctx->rules[insn->op2];
2075 ctx->rules[insn->op2] = rule = ir_match_insn(ctx, insn->op2);
2078 ctx->rules[insn->op2] = IR_FUSED | IR_SIMPLE | IR_LEA_OB;
2082 ctx->rules[insn->op2] = IR_FUSED | IR_SIMPLE | IR_LEA_SI;
2096 ir_match_fuse_load(ctx, insn->op2, ref);
2109 ir_match_fuse_load(ctx, insn->op2, ref);
2120 if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
2121 op2_insn = &ctx->ir_base[insn->op2];
2155 ir_match_fuse_load(ctx, insn->op2, ref);
2168 if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
2169 op2_insn = &ctx->ir_base[insn->op2];
2180 ir_match_fuse_load(ctx, insn->op2, ref);
2184 if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
2185 op2_insn = &ctx->ir_base[insn->op2];
2201 ir_match_fuse_load(ctx, insn->op2, ref);
2208 if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
2209 op2_insn = &ctx->ir_base[insn->op2];
2223 ir_match_fuse_load(ctx, insn->op2, ref);
2248 if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
2249 op2_insn = &ctx->ir_base[insn->op2];
2262 if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
2263 op2_insn = &ctx->ir_base[insn->op2];
2276 if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
2277 op2_insn = &ctx->ir_base[insn->op2];
2286 if (IR_IS_CONST_REF(insn->op2)) {
2288 op2_insn = &ctx->ir_base[insn->op2];
2312 if (IR_IS_CONST_REF(insn->op2)) {
2314 op2_insn = &ctx->ir_base[insn->op2];
2342 if (IR_IS_CONST_REF(insn->op2)) {
2343 const ir_insn *func = &ctx->ir_base[insn->op2];
2362 ir_match_fuse_load(ctx, insn->op2, ref);
2371 if (IR_IS_CONST_REF(insn->op2) && ctx->cfg_map[ref] == 1) {
2372 ir_insn *val = &ctx->ir_base[insn->op2];
2402 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2407 if (!IR_IS_CONST_REF(op_insn->op2)
2408 && ctx->rules[op_insn->op2] == (IR_FUSED|IR_SIMPLE|IR_LOAD)) {
2409 ctx->rules[op_insn->op2] = IR_LOAD_INT;
2413 && insn->op1 == op_insn->op2
2414 && ctx->ir_base[op_insn->op2].op == load_op
2415 && ctx->ir_base[op_insn->op2].op2 == insn->op2
2416 && ctx->use_lists[op_insn->op2].count == 2) {
2426 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2436 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2446 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2456 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2466 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2476 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2486 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2496 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2515 ir_match_fuse_addr(ctx, insn->op2);
2523 ir_match_fuse_addr(ctx, insn->op2);
2533 if (IR_REGSET_IN(IR_REGSET_UNION((ir_regset)ctx->fixed_regset, IR_REGSET_FIXED), insn->op2)) {
2538 if (IR_IS_TYPE_INT(ctx->ir_base[insn->op2].type)) {
2540 && ir_in_same_block(ctx, insn->op2)
2541 && ctx->use_lists[insn->op2].count == 1
2542 && IR_IS_TYPE_INT(ctx->ir_base[insn->op2].type)) {
2543 ir_insn *op_insn = &ctx->ir_base[insn->op2];
2553 && ctx->ir_base[op_insn->op1].op2 == insn->op3
2556 ctx->rules[insn->op2] = IR_FUSED | IR_BINOP_INT;
2560 && insn->op1 == op_insn->op2
2561 && ctx->ir_base[op_insn->op2].op == IR_RLOAD
2562 && ctx->ir_base[op_insn->op2].op2 == insn->op3
2563 && ctx->use_lists[op_insn->op2].count == 2) {
2566 ctx->rules[insn->op2] = IR_FUSED | IR_BINOP_INT;
2573 ir_match_fuse_load(ctx, insn->op2, ref);
2586 if (!insn->op2) {
2588 } else if (IR_IS_TYPE_INT(ctx->ir_base[insn->op2].type)) {
2594 if (!IR_IS_CONST_REF(insn->op2) && ctx->use_lists[insn->op2].count == 1) {
2595 op2_insn = &ctx->ir_base[insn->op2];
2598 if (IR_IS_CONST_REF(op2_insn->op2)
2599 && !IR_IS_SYM_CONST(ctx->ir_base[op2_insn->op2].op)
2600 && ctx->ir_base[op2_insn->op2].val.i64 == 0
2601 && op2_insn->op1 == insn->op2 - 1) { /* previous instruction */
2608 ctx->rules[insn->op2] = IR_FUSED | IR_SIMPLE | IR_NOP;
2610 } else if (insn->op2 == ref - 1 && /* previous instruction */
2621 ir_match_fuse_load(ctx, op1_insn->op2, ref);
2624 ctx->rules[insn->op2] = IR_FUSED | IR_CMP_INT;
2630 ctx->rules[insn->op2] = IR_FUSED | IR_CMP_INT;
2635 ctx->rules[insn->op2] = IR_FUSED | IR_CMP_FP;
2641 ctx->rules[insn->op2] = IR_FUSED | IR_TEST_INT;
2643 } else if (op2_insn->op == IR_OVERFLOW && ir_in_same_block(ctx, insn->op2)) {
2645 ctx->rules[insn->op2] = IR_FUSED | IR_SIMPLE | IR_OVERFLOW;
2649 if (IR_IS_TYPE_INT(ctx->ir_base[insn->op2].type)) {
2650 if (insn->op2 == ref - 1) { /* previous instruction */
2651 op2_insn = &ctx->ir_base[insn->op2];
2662 ctx->rules[insn->op2] = IR_BINOP_INT | IR_MAY_SWAP;
2664 ir_match_fuse_load(ctx, op2_insn->op2, ref);
2665 ctx->rules[insn->op2] = IR_BINOP_INT;
2671 && insn->op2 == ref - 2 /* previous instruction */
2672 && ctx->use_lists[insn->op2].count == 2
2673 && IR_IS_TYPE_INT(ctx->ir_base[insn->op2].type)) {
2676 if (store_insn->op == IR_STORE && store_insn->op3 == insn->op2) {
2677 ir_insn *op_insn = &ctx->ir_base[insn->op2];
2686 && ctx->ir_base[op_insn->op1].op2 == store_insn->op2) {
2691 ctx->rules[insn->op2] = IR_FUSED | IR_BINOP_INT;
2693 ir_match_fuse_addr(ctx, store_insn->op2);
2698 && ctx->ir_base[op_insn->op2].op == IR_LOAD
2699 && ctx->ir_base[op_insn->op2].op2 == store_insn->op2) {
2700 if (ir_in_same_block(ctx, op_insn->op2)
2701 && ctx->use_lists[op_insn->op2].count == 2
2702 && store_insn->op1 == op_insn->op2) {
2705 ctx->rules[insn->op2] = IR_FUSED | IR_BINOP_INT;
2707 ir_match_fuse_addr(ctx, store_insn->op2);
2715 ir_match_fuse_load(ctx, insn->op2, ref);
2740 if (!IR_IS_CONST_REF(insn->op2) && ctx->use_lists[insn->op2].count == 1) {
2741 op2_insn = &ctx->ir_base[insn->op2];
2744 && (insn->op2 == ref - 1 ||
2745 (insn->op2 == ctx->prev_ref[ref] - 1
2748 if (IR_IS_CONST_REF(op2_insn->op2)
2749 && !IR_IS_SYM_CONST(ctx->ir_base[op2_insn->op2].op)
2750 && ctx->ir_base[op2_insn->op2].val.i64 == 0) {
2751 if (op2_insn->op1 == insn->op2 - 1) { /* previous instruction */
2763 ir_match_fuse_load(ctx, op1_insn->op2, ref);
2767 ctx->rules[insn->op2] = IR_FUSED | IR_CMP_INT;
2771 && op2_insn->op1 == insn->op2 - 2 /* before previous instruction */
2774 ir_insn *store_insn = &ctx->ir_base[insn->op2 - 1];
2785 && ctx->ir_base[op_insn->op1].op2 == store_insn->op2) {
2792 ir_match_fuse_addr(ctx, store_insn->op2);
2793 ctx->rules[insn->op2 - 1] = IR_MEM_BINOP_INT;
2794 ctx->rules[insn->op2] = IR_SKIPPED | IR_NOP;
2798 && ctx->ir_base[op_insn->op2].op == IR_LOAD
2799 && ctx->ir_base[op_insn->op2].op2 == store_insn->op2) {
2800 if (ir_in_same_block(ctx, op_insn->op2)
2801 && ctx->use_lists[op_insn->op2].count == 2
2802 && store_insn->op1 == op_insn->op2) {
2807 ir_match_fuse_addr(ctx, store_insn->op2);
2808 ctx->rules[insn->op2 - 1] = IR_MEM_BINOP_INT;
2809 ctx->rules[insn->op2] = IR_SKIPPED | IR_NOP;
2819 ctx->rules[insn->op2] = IR_FUSED | IR_CMP_INT;
2824 ctx->rules[insn->op2] = IR_FUSED | IR_CMP_FP;
2830 ctx->rules[insn->op2] = IR_FUSED | IR_TEST_INT;
2832 } else if (op2_insn->op == IR_OVERFLOW && ir_in_same_block(ctx, insn->op2)) {
2834 ctx->rules[insn->op2] = IR_FUSED | IR_SIMPLE | IR_OVERFLOW;
2838 ir_match_fuse_load(ctx, insn->op2, ref);
2871 if ((ctx->ir_base[insn->op2].op == IR_ALLOCA) || (ctx->ir_base[insn->op2].op == IR_VADDR)) {
2872 ir_use_list *use_list = &ctx->use_lists[insn->op2];
2878 if (use_insn->op3 == insn->op2) {
2882 if (use_insn->op2 == insn->op2) {
3319 scale = ctx->ir_base[insn->op2].val.i32;
3326 scale = ctx->ir_base[insn->op2].val.i32 - 1;
3335 } else if (ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA) {
3336 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
3351 if (ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA) {
3352 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
3367 op2_insn = &ctx->ir_base[insn->op2];
3374 index_reg_ref = insn->op2 * sizeof(ir_ref) + 1;
3382 index_reg_ref = insn->op2 * sizeof(ir_ref) + 1;
3388 scale = ctx->ir_base[op1_insn->op2].val.i32;
3395 scale = ctx->ir_base[op1_insn->op2].val.i32 - 1;
3402 if (ir_rule(ctx, op1_insn->op2) == IR_STATIC_ALLOCA) {
3403 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[op1_insn->op2].op3);
3418 index_reg_ref = insn->op2 * sizeof(ir_ref) + 1;
3421 op2_insn = &ctx->ir_base[insn->op2];
3422 scale = ctx->ir_base[op2_insn->op2].val.i32;
3434 scale = ctx->ir_base[op1_insn->op2].val.i32;
3435 op2_insn = &ctx->ir_base[insn->op2];
3442 base_reg_ref = insn->op2 * sizeof(ir_ref) + 1;
3453 index_reg_ref = insn->op2 * sizeof(ir_ref) + 1;
3454 op2_insn = &ctx->ir_base[insn->op2];
3455 scale = ctx->ir_base[op2_insn->op2].val.i32;
3460 if (ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA) {
3461 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
3468 scale = ctx->ir_base[op1_insn->op2].val.i32;
3475 index_reg_ref = op1_insn->op2 * sizeof(ir_ref) + 1;
3476 op2_insn = &ctx->ir_base[op1_insn->op2];
3477 scale = ctx->ir_base[op2_insn->op2].val.i32;
3485 scale = ctx->ir_base[op1_insn->op2].val.i32;
3497 ir_insn *addr_insn = &ctx->ir_base[offset_insn->op2];
3553 ir_emit_load(ctx, IR_ADDR, reg, mem_insn->op2);
3556 } else if (IR_IS_CONST_REF(mem_insn->op2)) {
3557 return ir_fuse_addr_const(ctx, mem_insn->op2);
3559 return ir_fuse_addr(ctx, root, mem_insn->op2);
3819 ir_ref op2 = insn->op2;
3836 if (op1 == op2) {
3844 if (op1 != op2) {
3845 ir_emit_load(ctx, type, op2_reg, op2);
3873 } else if (IR_IS_CONST_REF(op2)) {
3874 int32_t val = ir_fuse_imm(ctx, op2);
3904 if (ir_rule(ctx, op2) & IR_FUSED) {
3905 mem = ir_fuse_load(ctx, def, op2);
3907 mem = ir_ref_spill_slot(ctx, op2);
3946 ir_ref op2 = insn->op2;
3949 int32_t val = ir_fuse_imm(ctx, op2);
3995 ir_ref op2 = insn->op2;
4016 if (op1 != op2) {
4017 ir_emit_load(ctx, type, op2_reg, op2);
4021 if (op1 == op2) {
4069 ir_insn *overflow_insn = &ctx->ir_base[insn->op2];
4107 ir_ref op2 = op_insn->op2;
4115 mem = ir_var_spill_slot(ctx, insn->op2);
4119 int32_t val = ir_fuse_imm(ctx, op2);
4145 ir_emit_load(ctx, type, op2_reg, op2);
4175 ir_insn *op_insn = &ctx->ir_base[insn->op2];
4177 ir_ref op2 = op_insn->op2;
4178 ir_reg op2_reg = ctx->regs[insn->op2][2];
4185 int32_t val = ir_fuse_imm(ctx, op2);
4209 ir_emit_load(ctx, type, op2_reg, op2);
4242 IR_ASSERT(IR_IS_CONST_REF(insn->op2));
4243 IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[insn->op2].op));
4258 uint32_t shift = IR_LOG2(ctx->ir_base[insn->op2].val.u64);
4266 uint32_t shift = IR_LOG2(ctx->ir_base[insn->op2].val.u64);
4271 uint64_t mask = ctx->ir_base[insn->op2].val.u64 - 1;
4300 uint32_t shift = IR_LOG2(ctx->ir_base[insn->op2].val.u64);
4301 int64_t offset = ctx->ir_base[insn->op2].val.u64 - 1;
4304 IR_ASSERT(IR_IS_CONST_REF(insn->op2));
4305 IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[insn->op2].op));
4364 uint32_t shift = IR_LOG2(ctx->ir_base[insn->op2].val.u64);
4365 uint64_t mask = ctx->ir_base[insn->op2].val.u64 - 1;
4368 IR_ASSERT(IR_IS_CONST_REF(insn->op2));
4369 IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[insn->op2].op));
4425 IR_ASSERT(IR_IS_CONST_REF(op_insn->op2));
4426 IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[op_insn->op2].op));
4432 mem = ir_var_spill_slot(ctx, insn->op2);
4436 uint32_t shift = IR_LOG2(ctx->ir_base[op_insn->op2].val.u64);
4439 uint32_t shift = IR_LOG2(ctx->ir_base[op_insn->op2].val.u64);
4443 uint64_t mask = ctx->ir_base[op_insn->op2].val.u64 - 1;
4465 ir_emit_load(ctx, type, op2_reg, insn->op2);
4475 ir_emit_load(ctx, type, IR_REG_RCX, insn->op2);
4515 ir_ref op2 = op_insn->op2;
4523 mem = ir_var_spill_slot(ctx, insn->op2);
4528 ir_emit_load(ctx, type, op2_reg, op2);
4534 ir_emit_load(ctx, type, IR_REG_RCX, op2);
4568 IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[insn->op2].op));
4569 IR_ASSERT(IR_IS_SIGNED_32BIT(ctx->ir_base[insn->op2].val.i64));
4570 shift = ctx->ir_base[insn->op2].val.i32;
4617 IR_ASSERT(IR_IS_CONST_REF(op_insn->op2));
4618 IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[op_insn->op2].op));
4619 IR_ASSERT(IR_IS_SIGNED_32BIT(ctx->ir_base[op_insn->op2].val.i64));
4620 shift = ctx->ir_base[op_insn->op2].val.i32;
4625 mem = ir_var_spill_slot(ctx, insn->op2);
5009 mem = ir_var_spill_slot(ctx, insn->op2);
5086 ir_ref op2 = insn->op2;
5103 if (op2_reg == IR_REG_NONE && op1 == op2) {
5108 ir_emit_load(ctx, type, op2_reg, op2);
5110 } else if (IR_IS_CONST_REF(op2)
5113 ir_emit_load(ctx, type, op2_reg, op2);
5120 if (ir_rule(ctx, op2) & IR_FUSED) {
5121 mem = ir_fuse_load(ctx, def, op2);
5123 mem = ir_ref_spill_slot(ctx, op2);
5131 if (ir_rule(ctx, op2) & IR_FUSED) {
5132 mem = ir_fuse_load(ctx, def, op2);
5134 mem = ir_ref_spill_slot(ctx, op2);
5153 if (ir_rule(ctx, op2) & IR_FUSED) {
5154 mem = ir_fuse_load(ctx, def, op2);
5156 mem = ir_ref_spill_slot(ctx, op2);
5169 if (ir_rule(ctx, op2) & IR_FUSED) {
5170 mem = ir_fuse_load(ctx, def, op2);
5172 mem = ir_ref_spill_slot(ctx, op2);
5332 ir_ref op2 = insn->op2;
5349 if (op1 == op2) {
5356 if (op1 != op2) {
5357 ir_emit_load(ctx, type, op2_reg, op2);
5382 } else if (IR_IS_CONST_REF(op2)) {
5383 int label = ir_const_label(ctx, op2);
5410 if (ir_rule(ctx, op2) & IR_FUSED) {
5411 mem = ir_fuse_load(ctx, def, op2);
5413 mem = ir_ref_spill_slot(ctx, op2);
5449 ir_ref op2 = insn->op2;
5463 if (op1 != op2) {
5464 ir_emit_load(ctx, type, op2_reg, op2);
5489 } else if (IR_IS_CONST_REF(op2)) {
5490 int label = ir_const_label(ctx, op2);
5517 if (ir_rule(ctx, op2) & IR_FUSED) {
5518 mem = ir_fuse_load(ctx, def, op2);
5520 mem = ir_ref_spill_slot(ctx, op2);
5550 …, ir_type type, ir_ref root, ir_insn *insn, ir_reg op1_reg, ir_ref op1, ir_reg op2_reg, ir_ref op2)
5558 …} else if (IR_IS_CONST_REF(op2) && !IR_IS_SYM_CONST(ctx->ir_base[op2].op) && ctx->ir_base[op2].val…
5560 } else if (IR_IS_CONST_REF(op2)) {
5561 int32_t val = ir_fuse_imm(ctx, op2);
5566 if (ir_rule(ctx, op2) & IR_FUSED) {
5567 mem = ir_fuse_load(ctx, root, op2);
5569 mem = ir_ref_spill_slot(ctx, op2);
5586 int32_t val = ir_fuse_imm(ctx, op2);
5596 ir_ref op2 = cmp_insn->op2;
5606 if (op1 != op2) {
5607 ir_emit_load(ctx, type, op2_reg, op2);
5611 ir_emit_cmp_int_common(ctx, type, root, cmp_insn, op1_reg, op1, op2_reg, op2);
5712 ir_ref op2 = insn->op2;
5724 if (op1 != op2) {
5725 ir_emit_load(ctx, type, op2_reg, op2);
5728 …if (IR_IS_CONST_REF(op2) && !IR_IS_SYM_CONST(ctx->ir_base[op2].op) && ctx->ir_base[op2].val.u64 ==…
5749 ir_emit_cmp_int_common(ctx, type, def, insn, op1_reg, op1, op2_reg, op2);
5763 ir_ref op2 = binop_insn->op2;
5776 if (op1 != op2) {
5777 ir_emit_load(ctx, type, op2_reg, op2);
5781 } else if (IR_IS_CONST_REF(op2)) {
5782 int32_t val = ir_fuse_imm(ctx, op2);
5808 if (ir_rule(ctx, op2) & IR_FUSED) {
5809 mem = ir_fuse_load(ctx, root, op2);
5811 mem = ir_ref_spill_slot(ctx, op2);
5828 if (op1 != op2) {
5829 ir_emit_load(ctx, type, op2_reg, op2);
5835 int32_t val = ir_fuse_imm(ctx, op2);
5870 ir_ref op1, op2;
5874 op2 = cmp_insn->op2;
5881 SWAP_REFS(op1, op2);
5896 if (op1 != op2) {
5897 ir_emit_load(ctx, type, op2_reg, op2);
5901 } else if (IR_IS_CONST_REF(op2)) {
5902 int label = ir_const_label(ctx, op2);
5908 if (ir_rule(ctx, op2) & IR_FUSED) {
5909 mem = ir_fuse_load(ctx, root, op2);
5911 mem = ir_ref_spill_slot(ctx, op2);
6132 ir_insn *cmp_insn = &ctx->ir_base[insn->op2];
6136 ir_ref op2 = cmp_insn->op2;
6137 ir_reg op1_reg = ctx->regs[insn->op2][1];
6138 ir_reg op2_reg = ctx->regs[insn->op2][2];
6146 if (op1 != op2) {
6147 ir_emit_load(ctx, type, op2_reg, op2);
6150 …if (IR_IS_CONST_REF(op2) && !IR_IS_SYM_CONST(ctx->ir_base[op2].op) && ctx->ir_base[op2].val.u64 ==…
6171 prev_insn = &ctx->ir_base[prev_insn->op2];
6172 if (prev_insn->op1 == cmp_insn->op1 && prev_insn->op2 == cmp_insn->op2) {
6178 ir_emit_cmp_int_common(ctx, type, def, cmp_insn, op1_reg, op1, op2_reg, op2);
6185 ir_ref op2 = insn->op2;
6186 ir_op op = ctx->ir_base[op2].op;
6189 op2 = ctx->ir_base[op2].op1;
6195 ir_emit_test_int_common(ctx, def, op2, op);
6201 ir_op op = ir_emit_cmp_fp_common(ctx, def, insn->op2, &ctx->ir_base[insn->op2]);
6207 ir_type type = ctx->ir_base[insn->op2].type;
6215 ir_emit_load(ctx, type, op2_reg, insn->op2);
6218 } else if (IR_IS_CONST_REF(insn->op2)) {
6222 if (ir_const_is_true(&ctx->ir_base[insn->op2])) {
6232 } else if (ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA) {
6243 if (ir_rule(ctx, insn->op2) & IR_FUSED) {
6244 mem = ir_fuse_load(ctx, def, insn->op2);
6246 mem = ir_ref_spill_slot(ctx, insn->op2);
6259 ir_ref op2 = insn->op2;
6269 if (op2 != op3) {
6272 ir_emit_load(ctx, type, op2_reg, op2);
6273 if (op1 == op2) {
6280 if (op1 == op2) {
6286 ir_emit_load(ctx, type, op2_reg, op2);
6288 if (op1 == op2) {
6299 if (op1_reg != IR_REG_NONE && op1 != op2 && op1 != op3 && IR_REG_SPILLED(op1_reg)) {
6327 } else if (IR_IS_CONST_REF(op2) && !IR_IS_SYM_CONST(ctx->ir_base[op2].op)) {
6329 ir_emit_mov_imm_int(ctx, type, def_reg, ctx->ir_base[op2].val.i64);
6331 ir_emit_load_ex(ctx, type, def_reg, op2, def);
6376 ir_emit_load_ex(ctx, type, def_reg, op2, def);
6403 ir_ref op2 = insn->op2;
6412 ir_emit_load(ctx, type, op2_reg, op2);
6413 if (op3 == op2) {
6417 if (op3_reg != IR_REG_NONE && op3 != op2 && IR_REG_SPILLED(op3_reg)) {
6440 } else if (IR_IS_CONST_REF(op2) && !IR_IS_SYM_CONST(ctx->ir_base[op2].op)) {
6442 ir_emit_mov_imm_int(ctx, type, def_reg, ctx->ir_base[op2].val.i64);
6444 ir_emit_load_ex(ctx, type, def_reg, op2, def);
6539 ir_emit_load_ex(ctx, type, def_reg, op2, def);
6567 ir_ref op2 = insn->op2;
6576 ir_emit_load(ctx, type, op2_reg, op2);
6577 if (op3 == op2) {
6581 if (op3_reg != IR_REG_NONE && op3 != op2 && IR_REG_SPILLED(op3_reg)) {
6639 ir_emit_load_ex(ctx, type, def_reg, op2, def);
6683 ir_type type = ctx->ir_base[insn->op2].type;
6688 ir_emit_load(ctx, type, IR_REG_INT_RET1, insn->op2);
6697 ir_type type = ctx->ir_base[insn->op2].type;
6704 ir_emit_load(ctx, type, IR_REG_FP_RET1, insn->op2);
6713 int32_t offset = ir_ref_spill_slot_offset(ctx, insn->op2, &fp);
7580 ir_insn *var_insn = &ctx->ir_base[insn->op2];
7606 ir_insn *var_insn = &ctx->ir_base[insn->op2];
7636 ir_insn *var_insn = &ctx->ir_base[insn->op2];
7678 IR_ASSERT(ctx->ir_base[insn->op2].type == IR_ADDR);
7679 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
7682 } else if (IR_IS_CONST_REF(insn->op2)) {
7683 mem = ir_fuse_addr_const(ctx, insn->op2);
7685 IR_ASSERT(ir_rule(ctx, insn->op2) & IR_FUSED);
7686 mem = ir_fuse_addr(ctx, def, insn->op2);
7717 IR_ASSERT(ctx->ir_base[insn->op2].type == IR_ADDR);
7718 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
7721 } else if (IR_IS_CONST_REF(insn->op2)) {
7722 mem = ir_fuse_addr_const(ctx, insn->op2);
7724 IR_ASSERT(ir_rule(ctx, insn->op2) & IR_FUSED);
7725 mem = ir_fuse_addr(ctx, def, insn->op2);
7752 IR_ASSERT(ctx->ir_base[insn->op2].type == IR_ADDR);
7753 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
7756 } else if (IR_IS_CONST_REF(insn->op2)) {
7757 mem = ir_fuse_addr_const(ctx, insn->op2);
7759 IR_ASSERT(ir_rule(ctx, insn->op2) & IR_FUSED);
7760 mem = ir_fuse_addr(ctx, ref, insn->op2);
7794 ir_ref op2 = cmp_insn->op2;
7801 IR_ASSERT(ctx->ir_base[insn->op2].type == IR_ADDR);
7802 ir_emit_load(ctx, IR_ADDR, addr_reg, insn->op2);
7805 } else if (IR_IS_CONST_REF(insn->op2)) {
7806 mem = ir_fuse_addr_const(ctx, insn->op2);
7808 IR_ASSERT(ir_rule(ctx, insn->op2) & IR_FUSED);
7809 mem = ir_fuse_addr(ctx, ref, insn->op2);
7818 if (op1 != op2) {
7819 ir_emit_load(ctx, type, op2_reg, op2);
7823 ir_emit_cmp_int_common(ctx, type, ref, cmp_insn, op1_reg, op1, op2_reg, op2);
7838 IR_ASSERT(ctx->ir_base[insn->op2].type == IR_ADDR);
7839 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
7842 } else if (IR_IS_CONST_REF(insn->op2)) {
7843 mem = ir_fuse_addr_const(ctx, insn->op2);
7845 IR_ASSERT(ir_rule(ctx, insn->op2) & IR_FUSED);
7846 mem = ir_fuse_addr(ctx, ref, insn->op2);
7874 ir_reg src_reg = insn->op2;
7912 ir_ref type = ctx->ir_base[insn->op2].type;
7919 ir_emit_load(ctx, type, op2_reg, insn->op2);
7930 ir_emit_load_ex(ctx, type, dst_reg, insn->op2, ref);
7944 if (IR_IS_CONST_REF(insn->op2)) {
7945 ir_insn *val = &ctx->ir_base[insn->op2];
7962 ir_type type = ctx->ir_base[insn->op2].type;
7969 ir_emit_load(ctx, type, op2_reg, insn->op2);
7975 ir_emit_load(ctx, type, def_reg, insn->op2);
7998 if (IR_IS_CONST_REF(insn->op2)) {
7999 ir_insn *val = &ctx->ir_base[insn->op2];
8016 ir_type type = ctx->ir_base[insn->op2].type;
8021 ir_emit_load(ctx, type, op2_reg, insn->op2);
8056 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
8093 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
8097 IR_ASSERT(ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA);
8099 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
8127 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
8131 IR_ASSERT(ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA);
8133 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
8194 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
8198 IR_ASSERT(ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA);
8200 op2_offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
8228 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
8232 IR_ASSERT(ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA);
8234 op2_offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
8276 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
8280 IR_ASSERT(ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA);
8282 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
8305 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
8309 IR_ASSERT(ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA);
8311 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
8367 type = ctx->ir_base[insn->op2].type;
8383 val = &ctx->ir_base[use_insn->op2];
8404 ir_emit_load(ctx, type, op2_reg, insn->op2);
8419 val = &ctx->ir_base[use_insn->op2];
8527 if (insn->op == IR_IJMP && IR_IS_CONST_REF(insn->op2)) {
8533 void *addr = ir_jmp_addr(ctx, insn, &ctx->ir_base[insn->op2]);
8555 val = &ctx->ir_base[use_insn->op2];
8904 if (IR_IS_CONST_REF(insn->op2)) {
8905 void *addr = ir_call_addr(ctx, insn, &ctx->ir_base[insn->op2]);
8932 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
8938 if (ir_rule(ctx, insn->op2) & IR_FUSED) {
8939 mem = ir_fuse_load(ctx, def, insn->op2);
8941 mem = ir_ref_spill_slot(ctx, insn->op2);
9044 if (IR_IS_CONST_REF(insn->op2)) {
9045 void *addr = ir_call_addr(ctx, insn, &ctx->ir_base[insn->op2]);
9072 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
9078 if (ir_rule(ctx, insn->op2) & IR_FUSED) {
9079 mem = ir_fuse_load(ctx, def, insn->op2);
9081 mem = ir_ref_spill_slot(ctx, insn->op2);
9094 if (IR_IS_CONST_REF(insn->op2)) {
9095 void *addr = ir_jmp_addr(ctx, insn, &ctx->ir_base[insn->op2]);
9109 } else if (ir_rule(ctx, insn->op2) & IR_FUSED) {
9110 ir_mem mem = ir_fuse_load(ctx, def, insn->op2);
9115 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
9119 ir_mem mem = ir_ref_spill_slot(ctx, insn->op2);
9223 } else if (next_insn->op == IR_IJMP && IR_IS_CONST_REF(next_insn->op2)) {
9224 void *target_addr = ir_jmp_addr(ctx, next_insn, &ctx->ir_base[next_insn->op2]);
9389 ir_type type = ctx->ir_base[insn->op2].type;
9393 if (IR_IS_CONST_REF(insn->op2)) {
9394 bool is_true = ir_ref_is_true(ctx, insn->op2);
9417 ir_emit_load(ctx, type, op2_reg, insn->op2);
9423 if (ir_rule(ctx, insn->op2) & IR_FUSED) {
9424 mem = ir_fuse_load(ctx, def, insn->op2);
9426 mem = ir_ref_spill_slot(ctx, insn->op2);
9466 ir_insn *cmp_insn = &ctx->ir_base[insn->op2];
9470 ir_ref op2 = cmp_insn->op2;
9471 ir_reg op1_reg = ctx->regs[insn->op2][1];
9472 ir_reg op2_reg = ctx->regs[insn->op2][2];
9481 if (op1 != op2) {
9482 ir_emit_load(ctx, type, op2_reg, op2);
9487 …if (IR_IS_CONST_REF(op2) && !IR_IS_SYM_CONST(ctx->ir_base[op2].op) && ctx->ir_base[op2].val.u64 ==…
9512 ir_emit_cmp_int_common(ctx, type, def, cmp_insn, op1_reg, op1, op2_reg, op2);
9523 ir_op op = ir_emit_cmp_fp_common(ctx, def, insn->op2, &ctx->ir_base[insn->op2]);
9537 ir_emit_test_int_common(ctx, def, insn->op2, op);
9544 ir_op op = ctx->ir_base[insn->op2].op;
9559 type = ctx->ir_base[ctx->ir_base[insn->op2].op1].type;
9654 | mov Ra(reg), aword [Ra(reg)+insn->op2]
9659 | mov Ra(reg), aword [Ra(reg)+insn->op2]
9664 | mov Ra(reg), aword [insn->op2]
9666 | mov Ra(reg), aword [insn->op2]
9672 | mov Ra(reg), aword [insn->op2]
9675 | mov Ra(reg), aword [Ra(reg)+insn->op2]
9681 | mov Ra(reg), aword [insn->op2]
9684 | mov Ra(reg), aword [Ra(reg)+insn->op2]
9814 if (IR_IS_CONST_REF(insn->op2)) {
9815 void *addr = ir_call_addr(ctx, insn, &ctx->ir_base[insn->op2]);
10166 && ir_is_same_mem_var(ctx, i, ctx->ir_base[insn->op2].op3)) {
10652 ir_op op = ctx->ir_base[insn->op2].op;
