Lines Matching refs:def
3785 static void ir_emit_binop_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
3792 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
3793 ir_reg op1_reg = ctx->regs[def][1];
3794 ir_reg op2_reg = ctx->regs[def][2];
3877 mem = ir_fuse_load(ctx, def, op2);
3907 if (IR_REG_SPILLED(ctx->regs[def][0])) {
3908 ir_emit_store(ctx, type, def, def_reg);
3912 static void ir_emit_imul3(ir_ctx *ctx, ir_ref def, ir_insn *insn)
3919 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
3920 ir_reg op1_reg = ctx->regs[def][1];
3950 mem = ir_fuse_load(ctx, def, op1);
3956 if (IR_REG_SPILLED(ctx->regs[def][0])) {
3957 ir_emit_store(ctx, type, def, def_reg);
3961 static void ir_emit_min_max_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
3968 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
3969 ir_reg op1_reg = ctx->regs[def][1];
3970 ir_reg op2_reg = ctx->regs[def][2];
4013 if (IR_REG_SPILLED(ctx->regs[def][0])) {
4014 ir_emit_store(ctx, type, def, def_reg);
4018 static void ir_emit_overflow(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4022 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
4032 if (IR_REG_SPILLED(ctx->regs[def][0])) {
4033 ir_emit_store(ctx, insn->type, def, def_reg);
4037 static void ir_emit_overflow_and_branch(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_…
4073 static void ir_emit_mem_binop_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4084 mem = ir_fuse_mem(ctx, def, def, insn, ctx->regs[def][2]);
4143 static void ir_emit_reg_binop_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4205 static void ir_emit_mul_div_mod_pwr2(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4211 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
4212 ir_reg op1_reg = ctx->regs[def][1];
4246 || if (ir_type_size[type] == 8 && ctx->regs[def][2] != IR_REG_NONE) {
4247 || ir_reg op2_reg = ctx->regs[def][2];
4259 if (IR_REG_SPILLED(ctx->regs[def][0])) {
4260 ir_emit_store(ctx, type, def, def_reg);
4264 static void ir_emit_sdiv_pwr2(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4270 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
4271 ir_reg op1_reg = ctx->regs[def][1];
4302 || ir_reg op2_reg = ctx->regs[def][2];
4322 if (IR_REG_SPILLED(ctx->regs[def][0])) {
4323 ir_emit_store(ctx, type, def, def_reg);
4327 static void ir_emit_smod_pwr2(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4333 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
4334 ir_reg op1_reg = ctx->regs[def][1];
4335 ir_reg tmp_reg = ctx->regs[def][3];
4369 || if (ir_type_size[type] == 8 && ctx->regs[def][2] != IR_REG_NONE) {
4370 || ir_reg op2_reg = ctx->regs[def][2];
4384 if (IR_REG_SPILLED(ctx->regs[def][0])) {
4385 ir_emit_store(ctx, type, def, def_reg);
4389 static void ir_emit_mem_mul_div_mod_pwr2(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4401 mem = ir_fuse_mem(ctx, def, def, insn, ctx->regs[def][2]);
4421 static void ir_emit_shift(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4426 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
4427 ir_reg op1_reg = ctx->regs[def][1];
4428 ir_reg op2_reg = ctx->regs[def][2];
4476 if (IR_REG_SPILLED(ctx->regs[def][0])) {
4477 ir_emit_store(ctx, type, def, def_reg);
4481 static void ir_emit_mem_shift(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4492 mem = ir_fuse_mem(ctx, def, def, insn, ctx->regs[def][2]);
4530 static void ir_emit_shift_const(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4537 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
4538 ir_reg op1_reg = ctx->regs[def][1];
4575 if (IR_REG_SPILLED(ctx->regs[def][0])) {
4576 ir_emit_store(ctx, type, def, def_reg);
4580 static void ir_emit_mem_shift_const(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4594 mem = ir_fuse_mem(ctx, def, def, insn, ctx->regs[def][2]);
4621 static void ir_emit_op_int(ir_ctx *ctx, ir_ref def, ir_insn *insn, uint32_t rule)
4627 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
4628 ir_reg op1_reg = ctx->regs[def][1];
4667 if (IR_REG_SPILLED(ctx->regs[def][0])) {
4668 ir_emit_store(ctx, type, def, def_reg);
4672 static void ir_emit_bit_count(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4678 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
4679 ir_reg op1_reg = ctx->regs[def][1];
4768 mem = ir_fuse_load(ctx, def, op1);
4834 if (IR_REG_SPILLED(ctx->regs[def][0])) {
4835 ir_emit_store(ctx, type, def, def_reg);
4839 static void ir_emit_ctpop(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4845 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
4846 ir_reg op1_reg = ctx->regs[def][1];
4847 ir_reg tmp_reg = ctx->regs[def][2];
4849 || ir_reg const_reg = ctx->regs[def][3];
4964 if (IR_REG_SPILLED(ctx->regs[def][0])) {
4965 ir_emit_store(ctx, type, def, def_reg);
4969 static void ir_emit_mem_op_int(ir_ctx *ctx, ir_ref def, ir_insn *insn, uint32_t rule)
4978 mem = ir_fuse_mem(ctx, def, def, insn, ctx->regs[def][2]);
4996 static void ir_emit_abs_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
5002 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
5003 ir_reg op1_reg = ctx->regs[def][1];
5017 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5018 ir_emit_store(ctx, type, def, def_reg);
5022 static void ir_emit_bool_not_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
5028 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
5029 ir_reg op1_reg = ctx->regs[def][1];
5047 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5048 ir_emit_store(ctx, type, def, def_reg);
5052 static void ir_emit_mul_div_mod(ir_ctx *ctx, ir_ref def, ir_insn *insn)
5059 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
5060 ir_reg op1_reg = ctx->regs[def][1];
5061 ir_reg op2_reg = ctx->regs[def][2];
5093 mem = ir_fuse_load(ctx, def, op2);
5104 mem = ir_fuse_load(ctx, def, op2);
5126 mem = ir_fuse_load(ctx, def, op2);
5142 mem = ir_fuse_load(ctx, def, op2);
5156 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5157 ir_emit_store(ctx, type, def, def_reg);
5160 ir_emit_store(ctx, type, def, IR_REG_RAX);
5170 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5171 ir_emit_store(ctx, type, def, def_reg);
5175 int32_t offset = ir_ref_spill_slot_offset(ctx, def, &fp);
5185 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5186 ir_emit_store(ctx, type, def, def_reg);
5189 ir_emit_store(ctx, type, def, IR_REG_RDX);
5207 static void ir_emit_op_fp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
5213 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
5214 ir_reg op1_reg = ctx->regs[def][1];
5293 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5294 ir_emit_store(ctx, insn->type, def, def_reg);
5298 static void ir_emit_binop_sse2(ir_ctx *ctx, ir_ref def, ir_insn *insn)
5305 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
5306 ir_reg op1_reg = ctx->regs[def][1];
5307 ir_reg op2_reg = ctx->regs[def][2];
5383 mem = ir_fuse_load(ctx, def, op2);
5410 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5411 ir_emit_store(ctx, insn->type, def, def_reg);
5415 static void ir_emit_binop_avx(ir_ctx *ctx, ir_ref def, ir_insn *insn)
5422 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
5423 ir_reg op1_reg = ctx->regs[def][1];
5424 ir_reg op2_reg = ctx->regs[def][2];
5490 mem = ir_fuse_load(ctx, def, op2);
5517 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5518 ir_emit_store(ctx, insn->type, def, def_reg);
5669 static void ir_emit_cmp_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
5677 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
5678 ir_reg op1_reg = ctx->regs[def][1];
5679 ir_reg op2_reg = ctx->regs[def][2];
5696 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5697 ir_emit_store(ctx, insn->type, def, def_reg);
5703 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5704 ir_emit_store(ctx, insn->type, def, def_reg);
5713 ir_emit_cmp_int_common(ctx, type, def, insn, op1_reg, op1, op2_reg, op2);
5715 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5716 ir_emit_store(ctx, insn->type, def, def_reg);
5805 static void ir_emit_testcc_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
5807 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
5810 ir_emit_test_int_common(ctx, def, insn->op1, insn->op);
5812 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5813 ir_emit_store(ctx, insn->type, def, def_reg);
5817 static void ir_emit_setcc_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
5819 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
5823 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5824 ir_emit_store(ctx, insn->type, def, def_reg);
5882 static void ir_emit_cmp_fp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
5886 ir_op op = ir_emit_cmp_fp_common(ctx, def, def, insn);
5887 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
5888 ir_reg tmp_reg = ctx->regs[def][3];
5937 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5938 ir_emit_store(ctx, insn->type, def, def_reg);
5942 static void ir_emit_jmp_true(ir_ctx *ctx, uint32_t b, ir_ref def, uint32_t next_block)
5954 static void ir_emit_jmp_false(ir_ctx *ctx, uint32_t b, ir_ref def, uint32_t next_block)
5966 static void ir_emit_jcc(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_t next_block, ui…
6086 static void ir_emit_cmp_and_branch_int(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_t…
6109 ir_emit_jmp_false(ctx, b, def, next_block);
6113 ir_emit_jmp_true(ctx, b, def, next_block);
6134 ir_emit_cmp_int_common(ctx, type, def, cmp_insn, op1_reg, op1, op2_reg, op2);
6136 ir_emit_jcc(ctx, b, def, insn, next_block, op, 1);
6139 static void ir_emit_test_and_branch_int(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_…
6151 ir_emit_test_int_common(ctx, def, op2, op);
6152 ir_emit_jcc(ctx, b, def, insn, next_block, op, 1);
6155 static void ir_emit_cmp_and_branch_fp(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_t …
6157 ir_op op = ir_emit_cmp_fp_common(ctx, def, insn->op2, &ctx->ir_base[insn->op2]);
6158 ir_emit_jcc(ctx, b, def, insn, next_block, op, 0);
6161 static void ir_emit_if_int(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_t next_block)
6164 ir_reg op2_reg = ctx->regs[def][2];
6200 mem = ir_fuse_load(ctx, def, insn->op2);
6206 ir_emit_jcc(ctx, b, def, insn, next_block, IR_NE, 1);
6209 static void ir_emit_cond(ir_ctx *ctx, ir_ref def, ir_insn *insn)
6218 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
6219 ir_reg op1_reg = ctx->regs[def][1];
6220 ir_reg op2_reg = ctx->regs[def][2];
6221 ir_reg op3_reg = ctx->regs[def][3];
6287 ir_emit_load_ex(ctx, type, def_reg, op2, def);
6297 ir_emit_load_ex(ctx, type, def_reg, op3, def);
6302 if (IR_REG_SPILLED(ctx->regs[def][0])) {
6303 ir_emit_store(ctx, type, def, def_reg);
6332 ir_emit_load_ex(ctx, type, def_reg, op2, def);
6345 ir_emit_load_ex(ctx, type, def_reg, op3, def);
6349 if (IR_REG_SPILLED(ctx->regs[def][0])) {
6350 ir_emit_store(ctx, type, def, def_reg);
6354 static void ir_emit_cond_cmp_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
6361 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
6362 ir_reg op2_reg = ctx->regs[def][2];
6363 ir_reg op3_reg = ctx->regs[def][3];
6378 ir_emit_cmp_int_common2(ctx, def, insn->op1, &ctx->ir_base[insn->op1]);
6400 ir_emit_load_ex(ctx, type, def_reg, op2, def);
6409 ir_emit_load_ex(ctx, type, def_reg, op3, def);
6495 ir_emit_load_ex(ctx, type, def_reg, op2, def);
6508 ir_emit_load_ex(ctx, type, def_reg, op3, def);
6513 if (IR_REG_SPILLED(ctx->regs[def][0])) {
6514 ir_emit_store(ctx, type, def, def_reg);
6518 static void ir_emit_cond_cmp_fp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
6525 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
6526 ir_reg op2_reg = ctx->regs[def][2];
6527 ir_reg op3_reg = ctx->regs[def][3];
6542 op = ir_emit_cmp_fp_common(ctx, def, insn->op1, &ctx->ir_base[insn->op1]);
6595 ir_emit_load_ex(ctx, type, def_reg, op2, def);
6608 ir_emit_load_ex(ctx, type, def_reg, op3, def);
6612 if (IR_REG_SPILLED(ctx->regs[def][0])) {
6613 ir_emit_store(ctx, type, def, def_reg);
6696 static void ir_emit_sext(ir_ctx *ctx, ir_ref def, ir_insn *insn)
6702 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
6703 ir_reg op1_reg = ctx->regs[def][1];
6763 mem = ir_fuse_load(ctx, def, insn->op1);
6799 if (IR_REG_SPILLED(ctx->regs[def][0])) {
6800 ir_emit_store(ctx, dst_type, def, def_reg);
6804 static void ir_emit_zext(ir_ctx *ctx, ir_ref def, ir_insn *insn)
6810 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
6811 ir_reg op1_reg = ctx->regs[def][1];
6874 mem = ir_fuse_load(ctx, def, insn->op1);
6909 if (IR_REG_SPILLED(ctx->regs[def][0])) {
6910 ir_emit_store(ctx, dst_type, def, def_reg);
6914 static void ir_emit_trunc(ir_ctx *ctx, ir_ref def, ir_insn *insn)
6918 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
6919 ir_reg op1_reg = ctx->regs[def][1];
6934 ir_emit_load_ex(ctx, dst_type, def_reg, insn->op1, def);
6936 if (IR_REG_SPILLED(ctx->regs[def][0])) {
6937 ir_emit_store(ctx, dst_type, def, def_reg);
6941 static void ir_emit_bitcast(ir_ctx *ctx, ir_ref def, ir_insn *insn)
6947 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
6948 ir_reg op1_reg = ctx->regs[def][1];
6962 ir_emit_load_ex(ctx, dst_type, def_reg, insn->op1, def);
6974 ir_emit_load_ex(ctx, dst_type, def_reg, insn->op1, def);
7016 mem = ir_fuse_load(ctx, def, insn->op1);
7063 mem = ir_fuse_load(ctx, def, insn->op1);
7071 if (IR_REG_SPILLED(ctx->regs[def][0])) {
7072 ir_emit_store(ctx, dst_type, def, def_reg);
7076 static void ir_emit_int2fp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7082 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
7083 ir_reg op1_reg = ctx->regs[def][1];
7184 mem = ir_fuse_load(ctx, def, insn->op1);
7232 if (IR_REG_SPILLED(ctx->regs[def][0])) {
7233 ir_emit_store(ctx, dst_type, def, def_reg);
7237 static void ir_emit_fp2int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7243 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
7244 ir_reg op1_reg = ctx->regs[def][1];
7334 mem = ir_fuse_load(ctx, def, insn->op1);
7374 if (IR_REG_SPILLED(ctx->regs[def][0])) {
7375 ir_emit_store(ctx, dst_type, def, def_reg);
7379 static void ir_emit_fp2fp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7385 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
7386 ir_reg op1_reg = ctx->regs[def][1];
7435 mem = ir_fuse_load(ctx, def, insn->op1);
7455 if (IR_REG_SPILLED(ctx->regs[def][0])) {
7456 ir_emit_store(ctx, dst_type, def, def_reg);
7460 static void ir_emit_copy_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7463 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
7464 ir_reg op1_reg = ctx->regs[def][1];
7478 ir_emit_store(ctx, type, def, op1_reg);
7482 if (def_reg != IR_REG_NONE && IR_REG_SPILLED(ctx->regs[def][0])) {
7483 ir_emit_store(ctx, type, def, def_reg);
7487 static void ir_emit_copy_fp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7490 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
7491 ir_reg op1_reg = ctx->regs[def][1];
7505 ir_emit_store(ctx, type, def, op1_reg);
7509 if (def_reg != IR_REG_NONE && IR_REG_SPILLED(ctx->regs[def][0])) {
7510 ir_emit_store(ctx, type, def, def_reg);
7514 static void ir_emit_vaddr(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7519 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
7529 if (IR_REG_SPILLED(ctx->regs[def][0])) {
7530 ir_emit_store(ctx, type, def, def_reg);
7534 static void ir_emit_vload(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7538 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
7542 if (ctx->use_lists[def].count == 1) {
7549 if (def_reg == IR_REG_NONE && ir_is_same_mem_var(ctx, def, var_insn->op3)) {
7555 if (IR_REG_SPILLED(ctx->regs[def][0])) {
7556 ir_emit_store(ctx, type, def, def_reg);
7619 static void ir_emit_load_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7622 ir_reg op2_reg = ctx->regs[def][2];
7623 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
7626 if (ctx->use_lists[def].count == 1) {
7642 mem = ir_fuse_addr(ctx, def, insn->op2);
7643 if (IR_REG_SPILLED(ctx->regs[def][0]) && ir_is_same_spill_slot(ctx, def, mem)) {
7644 if (!ir_may_avoid_spill_load(ctx, def, def)) {
7653 if (IR_REG_SPILLED(ctx->regs[def][0])) {
7654 ir_emit_store(ctx, type, def, def_reg);
7658 static void ir_emit_load_fp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7661 ir_reg op2_reg = ctx->regs[def][2];
7662 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
7665 if (ctx->use_lists[def].count == 1) {
7681 mem = ir_fuse_addr(ctx, def, insn->op2);
7682 if (IR_REG_SPILLED(ctx->regs[def][0]) && ir_is_same_spill_slot(ctx, def, mem)) {
7683 if (!ir_may_avoid_spill_load(ctx, def, def)) {
7692 if (IR_REG_SPILLED(ctx->regs[def][0])) {
7693 ir_emit_store(ctx, type, def, def_reg);
7828 static void ir_emit_rload(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7834 if (ctx->vregs[def]
7835 && ctx->live_intervals[ctx->vregs[def]]
7836 && ctx->live_intervals[ctx->vregs[def]]->stack_spill_pos != -1) {
7837 ir_emit_store(ctx, type, def, src_reg);
7840 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
7846 if (!insn->op3 || !ir_is_same_spill_slot(ctx, def, IR_MEM_BO(ctx->spill_base, insn->op3))) {
7847 ir_emit_store(ctx, type, def, src_reg);
7858 if (IR_REG_SPILLED(ctx->regs[def][0])
7859 && (!insn->op3 || !ir_is_same_spill_slot(ctx, def, IR_MEM_BO(ctx->spill_base, insn->op3)))) {
7860 ir_emit_store(ctx, type, def, def_reg);
7890 static void ir_emit_alloca(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7894 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
7896 if (ctx->use_lists[def].count == 1) {
7917 ir_reg op2_reg = ctx->regs[def][2];
7941 if (IR_REG_SPILLED(ctx->regs[def][0])) {
7942 ir_emit_store(ctx, insn->type, def, def_reg);
7945 ir_emit_store(ctx, IR_ADDR, def, IR_REG_STACK_POINTER);
7949 static void ir_emit_afree(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7971 ir_reg op2_reg = ctx->regs[def][2];
7986 static void ir_emit_block_begin(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7990 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
7992 if (ctx->use_lists[def].count == 1) {
7998 if (IR_REG_SPILLED(ctx->regs[def][0])) {
7999 ir_emit_store(ctx, IR_ADDR, def, def_reg);
8003 static void ir_emit_block_end(ir_ctx *ctx, ir_ref def, ir_insn *insn)
8007 ir_reg op2_reg = ctx->regs[def][2];
8018 static void ir_emit_frame_addr(ir_ctx *ctx, ir_ref def)
8022 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
8029 if (IR_REG_SPILLED(ctx->regs[def][0])) {
8030 ir_emit_store(ctx, IR_ADDR, def, def_reg);
8034 static void ir_emit_va_start(ir_ctx *ctx, ir_ref def, ir_insn *insn)
8041 ir_reg op2_reg = ctx->regs[def][2];
8042 ir_reg tmp_reg = ctx->regs[def][3];
8074 ir_reg op2_reg = ctx->regs[def][2];
8075 ir_reg tmp_reg = ctx->regs[def][3];
8136 static void ir_emit_va_copy(ir_ctx *ctx, ir_ref def, ir_insn *insn)
8141 ir_reg tmp_reg = ctx->regs[def][1];
8142 ir_reg op2_reg = ctx->regs[def][2];
8143 ir_reg op3_reg = ctx->regs[def][3];
8175 ir_reg tmp_reg = ctx->regs[def][1];
8176 ir_reg op2_reg = ctx->regs[def][2];
8177 ir_reg op3_reg = ctx->regs[def][3];
8217 static void ir_emit_va_arg(ir_ctx *ctx, ir_ref def, ir_insn *insn)
8223 ir_reg def_reg = ctx->regs[def][0];
8224 ir_reg op2_reg = ctx->regs[def][2];
8225 ir_reg tmp_reg = ctx->regs[def][3];
8244 if (IR_REG_SPILLED(ctx->regs[def][0])) {
8245 ir_emit_store(ctx, type, def, def_reg);
8252 ir_reg def_reg = ctx->regs[def][0];
8253 ir_reg op2_reg = ctx->regs[def][2];
8254 ir_reg tmp_reg = ctx->regs[def][3];
8299 if (IR_REG_SPILLED(ctx->regs[def][0])) {
8300 ir_emit_store(ctx, type, def, def_reg);
8308 static void ir_emit_switch(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn)
8320 ir_reg op2_reg = ctx->regs[def][2];
8321 ir_reg tmp_reg = ctx->regs[def][3];
8580 static int32_t ir_emit_arguments(ir_ctx *ctx, ir_ref def, ir_insn *insn, ir_reg tmp_reg)
8657 src_reg = ir_get_alocated_reg(ctx, def, j);
8725 src_reg = ir_get_alocated_reg(ctx, def, j);
8854 static void ir_emit_call_ex(ir_ctx *ctx, ir_ref def, ir_insn *insn, int32_t used_stack)
8883 ir_reg op2_reg = ctx->regs[def][2];
8895 mem = ir_fuse_load(ctx, def, insn->op2);
8920 def_reg = IR_REG_NUM(ctx->regs[def][0]);
8925 if (IR_REG_SPILLED(ctx->regs[def][0])) {
8926 ir_emit_store(ctx, insn->type, def, def_reg);
8928 } else if (ctx->use_lists[def].count > 1) {
8929 ir_emit_store(ctx, insn->type, def, IR_REG_INT_RET1);
8933 def_reg = IR_REG_NUM(ctx->regs[def][0]);
8939 if (IR_REG_SPILLED(ctx->regs[def][0])) {
8940 ir_emit_store(ctx, insn->type, def, def_reg);
8942 } else if (ctx->use_lists[def].count > 1) {
8943 ir_emit_store(ctx, insn->type, def, IR_REG_FP_RET1);
8946 if (ctx->use_lists[def].count > 1) {
8951 offset = ir_ref_spill_slot_offset(ctx, def, &fp);
8970 if (IR_REG_SPILLED(ctx->regs[def][0])) {
8971 ir_emit_store(ctx, insn->type, def, def_reg);
8980 static void ir_emit_call(ir_ctx *ctx, ir_ref def, ir_insn *insn)
8982 int32_t used_stack = ir_emit_arguments(ctx, def, insn, ctx->regs[def][1]);
8983 ir_emit_call_ex(ctx, def, insn, used_stack);
8986 static void ir_emit_tailcall(ir_ctx *ctx, ir_ref def, ir_insn *insn)
8990 int32_t used_stack = ir_emit_arguments(ctx, def, insn, ctx->regs[def][1]);
8993 ir_emit_call_ex(ctx, def, insn, used_stack);
9023 ir_reg op2_reg = ctx->regs[def][2];
9035 mem = ir_fuse_load(ctx, def, insn->op2);
9044 static void ir_emit_ijmp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
9048 ir_reg op2_reg = ctx->regs[def][2];
9066 ir_mem mem = ir_fuse_load(ctx, def, insn->op2);
9081 static bool ir_emit_guard_jcc(ir_ctx *ctx, uint32_t b, ir_ref def, uint32_t next_block, uint8_t op,…
9085 ir_insn *next_insn = &ctx->ir_base[def + 1];
9316 static bool ir_emit_guard(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_t next_block)
9320 ir_reg op2_reg = ctx->regs[def][2];
9356 mem = ir_fuse_load(ctx, def, insn->op2);
9372 return ir_emit_guard_jcc(ctx, b, def, next_block, op, addr, 1);
9394 static bool ir_emit_guard_cmp_int(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_t next…
9444 ir_emit_cmp_int_common(ctx, type, def, cmp_insn, op1_reg, op1, op2_reg, op2);
9450 return ir_emit_guard_jcc(ctx, b, def, next_block, op, addr, 1);
9453 static bool ir_emit_guard_cmp_fp(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_t next_…
9455 ir_op op = ir_emit_cmp_fp_common(ctx, def, insn->op2, &ctx->ir_base[insn->op2]);
9461 return ir_emit_guard_jcc(ctx, b, def, next_block, op, addr, 0);
9464 static bool ir_emit_guard_test_int(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_t nex…
9469 ir_emit_test_int_common(ctx, def, insn->op2, op);
9470 return ir_emit_guard_jcc(ctx, b, def, next_block, op, addr, 1);
9473 static bool ir_emit_guard_jcc_int(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_t next…
9481 return ir_emit_guard_jcc(ctx, b, def, next_block, op, addr, 1);
9484 static bool ir_emit_guard_overflow(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn)
9510 static void ir_emit_lea(ir_ctx *ctx, ir_ref def, ir_type type)
9514 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
9515 ir_mem mem = ir_fuse_addr(ctx, def, def);
9551 if (IR_REG_SPILLED(ctx->regs[def][0])) {
9552 ir_emit_store(ctx, type, def, def_reg);
9556 static void ir_emit_tls(ir_ctx *ctx, ir_ref def, ir_insn *insn)
9560 ir_reg reg = IR_REG_NUM(ctx->regs[def][0]);
9562 if (ctx->use_lists[def].count == 1) {
9604 if (IR_REG_SPILLED(ctx->regs[def][0])) {
9605 ir_emit_store(ctx, IR_ADDR, def, reg);
9609 static void ir_emit_sse_sqrt(ir_ctx *ctx, ir_ref def, ir_insn *insn)
9613 ir_reg op3_reg = ctx->regs[def][3];
9614 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
9626 if (IR_REG_SPILLED(ctx->regs[def][0])) {
9627 ir_emit_store(ctx, insn->type, def, def_reg);
9631 static void ir_emit_sse_round(ir_ctx *ctx, ir_ref def, ir_insn *insn, int round_op)
9635 ir_reg op3_reg = ctx->regs[def][3];
9636 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
9652 if (IR_REG_SPILLED(ctx->regs[def][0])) {
9653 ir_emit_store(ctx, insn->type, def, def_reg);
9657 static void ir_emit_exitcall(ir_ctx *ctx, ir_ref def, ir_insn *insn)
9661 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
9761 if (IR_REG_SPILLED(ctx->regs[def][0])) {
9762 ir_emit_store(ctx, insn->type, def, def_reg);
