Lines Matching refs:r4
45 |.define T3, [r4+0x50] // Used to store old value of IP
46 |.define T2, [r4+0x48] // Used to store old value of FP
47 |.define T1, [r4+0x40]
48 |.define A6, [r4+0x28] // preallocated slot for 6-th argument
49 |.define A5, [r4+0x20] // preallocated slot for 5-th argument
73 |.define T3, [r4+0x20] // Used to store old value of IP (CALL VM only)
74 |.define T2, [r4+0x18] // Used to store old value of FP (CALL VM only)
75 |.define T1, [r4]
87 |.define T3, [r4+0x18] // Used to store old value of IP (CALL VM only)
88 |.define T2, [r4+0x14] // Used to store old value of FP (CALL VM only)
89 |.define T1, [r4]
90 …|.define A4, [r4+0xC] // preallocated slots for arguments of "cdecl" functions (intersect wi…
91 |.define A3, [r4+0x8]
92 |.define A2, [r4+0x4]
93 |.define A1, [r4]
175 | add r4, HYBRID_SPAD
181 | sub r4, HYBRID_SPAD
1523 | sub r4, 4
1528 | add r4, 4
1560 | sub r4, 4
1565 | add r4, 4
1747 | add r4, SPAD // stack alignment
1752 | add r4, NR_SPAD // stack alignment
1773 | add r4, SPAD // stack alignment
1780 | add r4, NR_SPAD // stack alignment
1858 | add r4, SPAD
1863 | add r4, NR_SPAD
1901 | add r4, NR_SPAD // stack alignment
2011 | sub r4, 0x28
2013 | sub r4, 8
2015 | sub r4, 12
2027 | add r4, 0x28
2032 | add r4, 8
2034 | sub r4, 8
2038 | add r4, 28
2083 | sub r4, 8
2092 | add r4, 16
2112 | sub r4, 8
2121 | add r4, 16
2136 | sub r4, 8
2140 | add r4, 16
2358 | add r4, SPAD // stack alignment
2364 | add r4, NR_SPAD // stack alignment
2377 | sub r4, 16*8+16*8-8 /* CPU regs + SSE regs */
2378 | mov aword [r4+15*8], r15
2379 | mov aword [r4+11*8], r11
2380 | mov aword [r4+10*8], r10
2381 | mov aword [r4+9*8], r9
2382 | mov aword [r4+8*8], r8
2383 | mov aword [r4+7*8], rdi
2384 | mov aword [r4+6*8], rsi
2385 | mov aword [r4+2*8], rdx
2386 | mov aword [r4+1*8], rcx
2387 | mov aword [r4+0*8], rax
2388 | mov FCARG1a, aword [r4+16*8+16*8-8] // exit_num = POP
2389 | mov FCARG2a, r4
2390 | movsd qword [r4+16*8+15*8], xmm15
2391 | movsd qword [r4+16*8+14*8], xmm14
2392 | movsd qword [r4+16*8+13*8], xmm13
2393 | movsd qword [r4+16*8+12*8], xmm12
2394 | movsd qword [r4+16*8+11*8], xmm11
2395 | movsd qword [r4+16*8+10*8], xmm10
2396 | movsd qword [r4+16*8+9*8], xmm9
2397 | movsd qword [r4+16*8+8*8], xmm8
2398 | movsd qword [r4+16*8+7*8], xmm7
2399 | movsd qword [r4+16*8+6*8], xmm6
2400 | movsd qword [r4+16*8+5*8], xmm5
2401 | movsd qword [r4+16*8+4*8], xmm4
2402 | movsd qword [r4+16*8+3*8], xmm3
2403 | movsd qword [r4+16*8+2*8], xmm2
2404 | movsd qword [r4+16*8+1*8], xmm1
2405 | movsd qword [r4+16*8+0*8], xmm0
2407 | sub r4, 32 /* shadow space */
2410 | sub r4, 8*4+8*8-4 /* CPU regs + SSE regs */
2411 | mov aword [r4+7*4], edi
2412 | mov aword [r4+2*4], edx
2413 | mov aword [r4+1*4], ecx
2414 | mov aword [r4+0*4], eax
2415 | mov FCARG1a, aword [r4+8*4+8*8-4] // exit_num = POP
2416 | mov FCARG2a, r4
2417 | movsd qword [r4+8*4+7*8], xmm7
2418 | movsd qword [r4+8*4+6*8], xmm6
2419 | movsd qword [r4+8*4+5*8], xmm5
2420 | movsd qword [r4+8*4+4*8], xmm4
2421 | movsd qword [r4+8*4+3*8], xmm3
2422 | movsd qword [r4+8*4+2*8], xmm2
2423 | movsd qword [r4+8*4+1*8], xmm1
2424 | movsd qword [r4+8*4+0*8], xmm0
2432 | add r4, 16*8+16*8+32 /* CPU regs + SSE regs + shadow space */
2434 | add r4, 16*8+16*8 /* CPU regs + SSE regs */
2436 | add r4, 8*4+8*8 /* CPU regs + SSE regs */
2451 | add r4, SPAD // stack alignment
2456 | add r4, NR_SPAD // stack alignment
2480 | add r4, SPAD // stack alignment
2496 | add r4, NR_SPAD // stack alignment
2512 | add r4, SPAD // stack alignment
2517 | add r4, NR_SPAD // stack alignment
2539 | add aword [r4], n
2554 | add r4, SPAD // stack alignment
2564 | add r4, NR_SPAD // stack alignment
2579 | sub r4, 0x28
2581 | sub r4, 8
2583 | sub r4, 12
2593 | add r4, 0x28
2595 | add r4, 8
2597 | add r4, 12
2611 | sub r4, 0x28
2613 | sub r4, 8
2615 | sub r4, 12
2625 | add r4, 0x28
2627 | add r4, 8
2629 | add r4, 12
2643 | sub r4, 0x28
2645 | sub r4, 8
2647 | sub r4, 12
2657 | add r4, 0x28
2659 | add r4, 8
2661 | add r4, 12
2675 | sub r4, 0x28
2677 | sub r4, 8
2679 | sub r4, 12
2689 | add r4, 0x28
2691 | add r4, 8
2693 | add r4, 12
2707 | sub r4, 0x28
2709 | sub r4, 8
2711 | sub r4, 12
2721 | add r4, 0x28
2723 | add r4, 8
2725 | add r4, 12
2966 || sp_adj[SP_ADJ_ASSIGN] = sp_adj[SP_ADJ_RET] + 0x28; // sub r4, 0x28
2968 || sp_adj[SP_ADJ_ASSIGN] = sp_adj[SP_ADJ_RET] + 8; // sub r4, 8
2970 || sp_adj[SP_ADJ_ASSIGN] = sp_adj[SP_ADJ_RET] + 12; // sub r4, 12
2975 || sp_adj[SP_ADJ_JIT] = sp_adj[SP_ADJ_VM] + HYBRID_SPAD; // sub r4, HYBRID_SPAD
2980 || sp_adj[SP_ADJ_JIT] = sp_adj[SP_ADJ_RET] + SPAD; // sub r4, SPAD
2982 || sp_adj[SP_ADJ_JIT] = sp_adj[SP_ADJ_RET] + NR_SPAD; // sub r4, NR_SPAD
3013 | sub r4, SPAD // stack alignment
3015 | sub r4, NR_SPAD // stack alignment
3393 // sub r4, HYBRID_SPAD
3396 // sub r4, HYBRID_SPAD
3400 // sub r4, SPAD // stack alignment
3407 // sub r4, NR_SPAD // stack alignment
3446 | add r4, SPAD // stack alignment
3465 | add r4, NR_SPAD // stack alignment
3743 | add r4, SPAD // stack alignment
3748 | add r4, NR_SPAD // stack alignment
4986 | sub r4, 12
5002 | add r4, 12
5401 | sub r4, 12
5421 | add r4, 12
5510 | sub r4, 12
5519 | add r4, 12
5548 | sub r4, 12
5554 | add r4, 12
6017 | sub r4, 12
6022 | add r4, 12
6049 | sub r4, 12
6054 | add r4, 12
6705 | sub r4, 8
6727 | add r4, 8
6901 | sub r4, 12
6911 | add r4, 12
6980 | sub r4, 8
6986 | add r4, 8
7042 | sub r4, 12
7053 | add r4, 12
9590 | sub r4, 12
9600 | add r4, 12
9674 | sub r4, 12
9683 | add r4, 12
10229 | add r4, SPAD // stack alignment
10234 | add r4, NR_SPAD // stack alignment
11536 | add r4, SPAD // stack alignment
11552 | add r4, NR_SPAD // stack alignment
11558 | add r4, NR_SPAD // stack alignment
11927 | sub r4, 12
11932 | add r4, 12
11964 | sub r4, 12
11973 | add r4, 12
12307 | sub r4, 12
12325 | add r4, 12
13018 | sub r4, 12
13023 | add r4, 12
13118 | sub r4, 12
13123 | add r4, 12
13537 | sub r4, 12
13557 | add r4, 12
13762 | sub r4, 8
13791 | add r4, 8
13998 | sub r4, 12
14008 | add r4, 12
14030 | sub r4, 8
14038 | add r4, 8
14085 | sub r4, 12
14095 | add r4, 12
14197 | sub r4, 4
14208 | add r4, 4
14394 | sub r4, 8
14406 | add r4, 8
14464 | sub r4, 8
14476 | add r4, 8
14525 | sub r4, 4
14540 | add r4, 4
15235 | sub r4, 8
15241 | add r4, 8
