Lines Matching refs:OPC1
113 #define OPC1(opcode) ((opcode) << 30) macro
118 #define ADD (OPC1(0x2) | OPC3(0x00))
119 #define ADDC (OPC1(0x2) | OPC3(0x08))
120 #define AND (OPC1(0x2) | OPC3(0x01))
121 #define ANDN (OPC1(0x2) | OPC3(0x05))
122 #define CALL (OPC1(0x1))
123 #define FABSS (OPC1(0x2) | OPC3(0x34) | DOP(0x09))
124 #define FADDD (OPC1(0x2) | OPC3(0x34) | DOP(0x42))
125 #define FADDS (OPC1(0x2) | OPC3(0x34) | DOP(0x41))
126 #define FCMPD (OPC1(0x2) | OPC3(0x35) | DOP(0x52))
127 #define FCMPS (OPC1(0x2) | OPC3(0x35) | DOP(0x51))
128 #define FDIVD (OPC1(0x2) | OPC3(0x34) | DOP(0x4e))
129 #define FDIVS (OPC1(0x2) | OPC3(0x34) | DOP(0x4d))
130 #define FDTOI (OPC1(0x2) | OPC3(0x34) | DOP(0xd2))
131 #define FDTOS (OPC1(0x2) | OPC3(0x34) | DOP(0xc6))
132 #define FITOD (OPC1(0x2) | OPC3(0x34) | DOP(0xc8))
133 #define FITOS (OPC1(0x2) | OPC3(0x34) | DOP(0xc4))
134 #define FMOVS (OPC1(0x2) | OPC3(0x34) | DOP(0x01))
135 #define FMULD (OPC1(0x2) | OPC3(0x34) | DOP(0x4a))
136 #define FMULS (OPC1(0x2) | OPC3(0x34) | DOP(0x49))
137 #define FNEGS (OPC1(0x2) | OPC3(0x34) | DOP(0x05))
138 #define FSTOD (OPC1(0x2) | OPC3(0x34) | DOP(0xc9))
139 #define FSTOI (OPC1(0x2) | OPC3(0x34) | DOP(0xd1))
140 #define FSUBD (OPC1(0x2) | OPC3(0x34) | DOP(0x46))
141 #define FSUBS (OPC1(0x2) | OPC3(0x34) | DOP(0x45))
142 #define JMPL (OPC1(0x2) | OPC3(0x38))
143 #define NOP (OPC1(0x0) | OPC2(0x04))
144 #define OR (OPC1(0x2) | OPC3(0x02))
145 #define ORN (OPC1(0x2) | OPC3(0x06))
146 #define RDY (OPC1(0x2) | OPC3(0x28) | S1A(0))
147 #define RESTORE (OPC1(0x2) | OPC3(0x3d))
148 #define SAVE (OPC1(0x2) | OPC3(0x3c))
149 #define SETHI (OPC1(0x0) | OPC2(0x04))
150 #define SLL (OPC1(0x2) | OPC3(0x25))
151 #define SLLX (OPC1(0x2) | OPC3(0x25) | (1 << 12))
152 #define SRA (OPC1(0x2) | OPC3(0x27))
153 #define SRAX (OPC1(0x2) | OPC3(0x27) | (1 << 12))
154 #define SRL (OPC1(0x2) | OPC3(0x26))
155 #define SRLX (OPC1(0x2) | OPC3(0x26) | (1 << 12))
156 #define SUB (OPC1(0x2) | OPC3(0x04))
157 #define SUBC (OPC1(0x2) | OPC3(0x0c))
158 #define TA (OPC1(0x2) | OPC3(0x3a) | (8 << 25))
159 #define WRY (OPC1(0x2) | OPC3(0x30) | DA(0))
160 #define XOR (OPC1(0x2) | OPC3(0x03))
161 #define XNOR (OPC1(0x2) | OPC3(0x07))
168 #define BICC (OPC1(0x0) | OPC2(0x2))
169 #define FBFCC (OPC1(0x0) | OPC2(0x6))
171 #define SDIV (OPC1(0x2) | OPC3(0x0f))
172 #define SMUL (OPC1(0x2) | OPC3(0x0b))
173 #define UDIV (OPC1(0x2) | OPC3(0x0e))
174 #define UMUL (OPC1(0x2) | OPC3(0x0a))
482 /* u w s */ ARCH_32_64(OPC1(3) | OPC3(0x04) /* stw */, OPC1(3) | OPC3(0x0e) /* stx */),
483 /* u w l */ ARCH_32_64(OPC1(3) | OPC3(0x00) /* lduw */, OPC1(3) | OPC3(0x0b) /* ldx */),
484 /* u b s */ OPC1(3) | OPC3(0x05) /* stb */,
485 /* u b l */ OPC1(3) | OPC3(0x01) /* ldub */,
486 /* u h s */ OPC1(3) | OPC3(0x06) /* sth */,
487 /* u h l */ OPC1(3) | OPC3(0x02) /* lduh */,
488 /* u i s */ OPC1(3) | OPC3(0x04) /* stw */,
489 /* u i l */ OPC1(3) | OPC3(0x00) /* lduw */,
491 /* s w s */ ARCH_32_64(OPC1(3) | OPC3(0x04) /* stw */, OPC1(3) | OPC3(0x0e) /* stx */),
492 /* s w l */ ARCH_32_64(OPC1(3) | OPC3(0x00) /* lduw */, OPC1(3) | OPC3(0x0b) /* ldx */),
493 /* s b s */ OPC1(3) | OPC3(0x05) /* stb */,
494 /* s b l */ OPC1(3) | OPC3(0x09) /* ldsb */,
495 /* s h s */ OPC1(3) | OPC3(0x06) /* sth */,
496 /* s h l */ OPC1(3) | OPC3(0x0a) /* ldsh */,
497 /* s i s */ OPC1(3) | OPC3(0x04) /* stw */,
498 /* s i l */ ARCH_32_64(OPC1(3) | OPC3(0x00) /* lduw */, OPC1(3) | OPC3(0x08) /* ldsw */),
500 /* d s */ OPC1(3) | OPC3(0x27),
501 /* d l */ OPC1(3) | OPC3(0x23),
502 /* s s */ OPC1(3) | OPC3(0x24),
503 /* s l */ OPC1(3) | OPC3(0x20),
