Searched refs:IR_BB_ENTRY (Results 1 – 7 of 7) sorted by relevance
217 bb->flags |= IR_BB_ENTRY; in ir_build_cfg()740 if (blocks[succ_b].flags & IR_BB_ENTRY) { in ir_build_dominators_tree()743 IR_ASSERT(blocks[ctx->cfg_edges[bb->successors + 1]].flags & IR_BB_ENTRY); in ir_build_dominators_tree()1033 if (bb->flags & (IR_BB_ENTRY|IR_BB_LOOP_WITH_ENTRY)) { in ir_find_loops()1051 if ((bb->flags & (IR_BB_START|IR_BB_ENTRY|IR_BB_EMPTY)) == IR_BB_EMPTY) { in _ir_skip_empty_blocks()1186 is_empty = (bb->flags & (IR_BB_START|IR_BB_ENTRY|IR_BB_EMPTY)) == IR_BB_EMPTY; in ir_dump_cfg_freq_graph()1303 if ((bb->flags & (IR_BB_START|IR_BB_ENTRY|IR_BB_EMPTY)) == IR_BB_EMPTY) { in ir_schedule_blocks_bottom_up()1409 && (successor1_bb->flags & (IR_BB_START|IR_BB_ENTRY|IR_BB_EMPTY)) != IR_BB_EMPTY) { in ir_schedule_blocks_bottom_up()1572 IR_ASSERT(ctx->cfg_blocks[b].flags & IR_BB_ENTRY); in ir_schedule_blocks_bottom_up()1582 } while ((bb->flags & (IR_BB_START|IR_BB_ENTRY|IR_BB_EMPTY)) == IR_BB_EMPTY); in ir_schedule_blocks_bottom_up()[all …]
250 if (bb->flags & IR_BB_ENTRY) { in ir_dump_cfg_block()511 if ((bb->flags & (IR_BB_START|IR_BB_ENTRY|IR_BB_EMPTY)) == IR_BB_EMPTY) { in ir_dump_codegen()
981 if (UNEXPECTED(bb->flags & IR_BB_ENTRY)) { in ir_match()997 if (EXPECTED(!(bb->flags & IR_BB_ENTRY))) { in ir_match()
647 if (EXPECTED(succ > b) && EXPECTED(!(ctx->cfg_blocks[succ].flags & IR_BB_ENTRY))) { in ir_compute_live_ranges()656 if (EXPECTED(succ > b) && EXPECTED(!(ctx->cfg_blocks[succ].flags & IR_BB_ENTRY))) { in ir_compute_live_ranges()1058 if (bb->flags & IR_BB_ENTRY) { in ir_compute_live_sets()3817 if (bb->flags & (IR_BB_ENTRY|IR_BB_START)) { in needs_spill_reload()
1071 #define IR_BB_ENTRY (1<<2) macro
5886 if ((bb->flags & (IR_BB_START|IR_BB_ENTRY|IR_BB_EMPTY)) == IR_BB_EMPTY) {5896 if (bb->flags & IR_BB_ENTRY) {6028 if (ctx->cfg_blocks[succ].flags & IR_BB_ENTRY) {6031 IR_ASSERT(ctx->cfg_blocks[ctx->cfg_edges[bb->successors + 1]].flags & IR_BB_ENTRY);
9010 if (ctx->cfg_blocks[target].flags & IR_BB_ENTRY) {9013 IR_ASSERT(ctx->cfg_blocks[ctx->cfg_edges[bb->successors + 1]].flags & IR_BB_ENTRY);10317 if ((bb->flags & (IR_BB_START|IR_BB_ENTRY|IR_BB_EMPTY)) == IR_BB_EMPTY) {10327 if (bb->flags & IR_BB_ENTRY) {10552 if (ctx->cfg_blocks[succ].flags & IR_BB_ENTRY) {10555 IR_ASSERT(ctx->cfg_blocks[ctx->cfg_edges[bb->successors + 1]].flags & IR_BB_ENTRY);
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