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/openssl/doc/man3/
H A DOPENSSL_instrument_bus.pod10 size_t OPENSSL_instrument_bus(unsigned int *vector, size_t num);
11 size_t OPENSSL_instrument_bus2(unsigned int *vector, size_t num, size_t max);
21 addition probes are added to B<vector> elements in atomic or
23 multi-processor systems. This also means that B<vector[num]> should be
32 performs at most B<max> probes in attempt to fill the B<vector[num]>,
H A DOPENSSL_s390xcap.pod5 OPENSSL_s390xcap - the IBM z processor capabilities vector
14 extensions are denoted by individual bits in the capabilities vector.
16 and by the QUERY functions are stored in the vector.
20 application. After initialization, the capability vector is ANDed bitwise
79 #129 1<<62 vector facility
80 #134 1<<57 vector packed decimal facility
81 #135 1<<56 vector enhancements facility 1
190 Disables the vector facility:
H A DOPENSSL_riscvcap.pod5 OPENSSL_riscvcap - the RISC-V processor capabilities vector
15 vector. For Linux platform, when libcrypto is initialized, the results
17 in the vector. Otherwise all capabilities are disabled.
33 zba/zbb/zbs would not be implied in the capability vector.
198 Only enable the vector extension:
H A DSSL_CTX_set_alpn_select_cb.pod64 vector in protocol-list format. The value of the B<out>, B<outlen> vector
66 B<inlen> vector. The B<out> buffer may point directly into B<in>, or to a
130 The protocol-lists must be in wire-format, which is defined as a vector of
134 vector is not in the vector itself, but in a separate variable.
138 unsigned char vector[] = {
142 unsigned int length = sizeof(vector);
H A DOPENSSL_ia32cap.pod5 OPENSSL_ia32cap - the x86[_64] processor capabilities vector
14 extensions are denoted by individual bits in capability vector returned
16 with EAX=1 input value (see Intel Application Note #241618). This vector
69 enable XMM registers. Historically address of the capability vector copy
86 The capability vector is further extended with EBX value returned by
H A DBF_encrypt.pod59 or decryption (B<BF_DECRYPT>) shall be performed. The vector pointed at by
64 all operate on variable length data. They all take an initialization vector
82 long initialization vector.
88 8 byte long initialization vector. B<num> must point at an integer which must
96 encryption. They encrypt/decrypt the first 64 bits of the vector pointed by
H A DSSL_CTX_set_tlsext_ticket_key_cb.pod66 The initialization vector I<iv> should be a random value. The cipher context
67 I<ctx> should use the initialisation vector I<iv>. The cipher context can be
77 I<ctx> will be set with the retrieved parameters and the initialization vector
H A DEVP_CIPHER_CTX_get_original_iv.pod27 initialization vector (IV) information from the B<EVP_CIPHER_CTX> into the
H A DPEM_read_bio_PrivateKey.pod427 used by EVP_get_cipherbyname() and an initialization vector used by the
432 initialization vector is passed to EVP_BytesToKey() as the I<salt>
434 (regardless of the size of the initialization vector). The user's
440 vector is then used to decrypt the encrypted data. The I<iv> produced by
H A DDES_random_key.pod168 and initialization vector provided by the I<ivec> argument. If the
258 using I<sched> for the key and I<iv> as a starting vector. The actual
H A DUI_new.pod78 reference to a UI_METHOD, which is an ordered vector of functions that
/openssl/test/
H A Dmodes_internal_test.c195 unsigned char cleartext[64], ciphertext[64], vector[64]; in execute_cts128() local
200 tail = fixture->last_blocks_correction(orig_vector, vector, len); in execute_cts128()
207 || !TEST_mem_eq(ciphertext, len, vector, len) in execute_cts128()
208 || !TEST_mem_eq(iv, sizeof(iv), vector + len - tail, sizeof(iv))) in execute_cts128()
218 || !TEST_mem_eq(iv, sizeof(iv), vector + len - tail, sizeof(iv))) in execute_cts128()
227 || !TEST_mem_eq(ciphertext, len, vector, len) in execute_cts128()
228 || !TEST_mem_eq(iv, sizeof(iv), vector + len - tail, sizeof(iv))) in execute_cts128()
238 || !TEST_mem_eq(iv, sizeof(iv), vector + len - tail, sizeof(iv))) in execute_cts128()
H A Ddhkem_test.inc500 /* Test vector from https://github.com/cfrg/draft-irtf-cfrg-hpke */
/openssl/test/recipes/30-test_evp_data/
H A Devpmd_whirlpool.txt14 Title = Whirlpool (from ISO/IEC 10118-3 test vector set)
H A Devpciph_aes_common.txt648 # Self-generated vector to trigger false carry on big-endian platforms
H A Devprand.txt15 # Test vector from NISTs CAVP tool
/openssl/doc/man7/
H A DEVP_KDF-SCRYPT.pod83 This example derives a 64-byte long test vector using scrypt with the password
/openssl/crypto/aes/asm/
H A Dbsaes-armv8.pl1014 // x4 -> 128-bit initialisation vector (or preceding 128-bit block of ciphertext if continuing af…
1018 // Initialisation vector overwritten with last quadword of ciphertext
1474 // x4 -> key2 (used to encrypt the initial vector to yield the initial tweak)
1475 // x5 -> 16-byte initial vector (typically, sector number)
/openssl/Configurations/
H A Ddescrip.mms.tmpl1258 die "More than one symbol vector" if scalar @defs > 1;
1308 die "More than one symbol vector" if scalar @defs > 1;
/openssl/
H A DNEWS.md211 * Various optimizations for cryptographic routines using RISC-V vector crypto
281 * Fixed POLY1305 MAC implementation corrupting vector registers on PowerPC
H A DINSTALL.md986 the machine code will be executed is taken solely on CPU capability vector. This
H A DCHANGES.md457 * Various optimizations for cryptographic routines using RISC-V vector crypto
551 for PowerPC CPUs saves the contents of vector registers in different
552 order than they are restored. Thus the contents of some of these vector
561 application process. However unless the compiler uses the vector registers
1943 S390X capability vector to zero. This simplifies testing of different code
6090 the standard OpenSSL PRNG: set additional data to a date time vector.
9097 - x86[_64]: SSSE3 support (SHA1, vector-permutation AES);
/openssl/providers/fips/
H A Dself_test_data.inc413 * Input parameters from RFC 6070, vector 5 (because it is the only one with

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