Lines Matching refs:SRL
301 #define SRL (HI(0) | LO(2)) macro
1578 …FAIL_IF(push_inst(compiler, SELECT_OP(DSRL, SRL) | T(TMP_REG1) | D(TMP_REG1) | SH_IMM(1), DR(TMP_R… in emit_clz_ctz()
1652 FAIL_IF(push_inst(compiler, SRL | T(src) | D(TMP_REG1) | SH_IMM(16), DR(TMP_REG1))); in emit_rev()
1658 FAIL_IF(push_inst(compiler, SRL | T(dst) | D(TMP_REG1) | SH_IMM(8), DR(TMP_REG1))); in emit_rev()
1687 …FAIL_IF(push_inst(compiler, SELECT_OP(DSRL, SRL) | T(src) | D(TMP_REG1) | SH_IMM(8), DR(TMP_REG1))… in emit_rev16()
1690 …FAIL_IF(push_inst(compiler, (GET_OPCODE(op) == SLJIT_REV_U16 ? SELECT_OP(DSRL32, SRL) : SELECT_OP(… in emit_rev16()
1810 …FAIL_IF(push_inst(compiler, SELECT_OP(DSRL32, SRL) | T(TMP_REG1) | D(TMP_REG1) | SH_IMM(SELECT_OP(… in emit_single_op()
1885 …FAIL_IF(push_inst(compiler, SELECT_OP(DSRL32, SRL) | T(TMP_REG1) | D(TMP_REG1) | SH_IMM(31), DR(TM… in emit_single_op()
2028 …FAIL_IF(push_inst(compiler, SELECT_OP(DSRL32, SRL) | T(TMP_REG1) | D(TMP_REG1) | SH_IMM(31), DR(TM… in emit_single_op()
2122 EMIT_SHIFT(DSRL, DSRL32, SRL, DSRLV, SRLV); in emit_single_op()
2172 op_imm = (GET_OPCODE(op) == SLJIT_ROTL) ? SLL : SRL; in emit_single_op()
2176 op_imm = (GET_OPCODE(op) == SLJIT_ROTL) ? SRL : SLL; in emit_single_op()
2706 ins2 = SELECT_OP3(op, src3w, DSRL, DSRL32, SRL); in sljit_emit_shift_into()
2708 ins1 = SELECT_OP3(op, src3w, DSRL, DSRL32, SRL); in sljit_emit_shift_into()
2727 ins1 = SELECT_OP(DSRL, SRL); in sljit_emit_shift_into()
2952 FAIL_IF(push_inst(compiler, SRL | T(TMP_REG2) | D(TMP_REG2) | SH_IMM(1), DR(TMP_REG2))); in sljit_emit_fop1_conv_f64_from_uw()
3013 FAIL_IF(push_inst(compiler, SRL | T(src) | D(TMP_REG1) | SH_IMM(1), DR(TMP_REG1))); in sljit_emit_fop1_conv_f64_from_uw()
3651 FAIL_IF(push_inst(compiler, SRL | TA(dst_ar) | DA(dst_ar) | SH_IMM(23), dst_ar)); in sljit_emit_op_flags()
