Lines Matching refs:op1
72 |.macro ASM_EXPAND_OP_MEM, MACRO, op, type, op1
74 || int32_t offset = IR_MEM_OFFSET(op1);
75 || int32_t base = IR_MEM_BASE(op1);
76 || int32_t index = IR_MEM_INDEX(op1);
77 || int32_t scale = IR_MEM_SCALE(op1);
113 |.macro ASM_EXPAND_OP1_MEM, MACRO, op, type, op1, op2
115 || int32_t offset = IR_MEM_OFFSET(op1);
116 || int32_t base = IR_MEM_BASE(op1);
117 || int32_t index = IR_MEM_INDEX(op1);
118 || int32_t scale = IR_MEM_SCALE(op1);
154 |.macro ASM_EXPAND_OP2_MEM, MACRO, op, type, op1, op2
162 | MACRO op, type, op1, [offset]
164 | MACRO op, type, op1, [Ra(base)+offset]
168 | MACRO op, type, op1, [Ra(index)*8+offset]
170 | MACRO op, type, op1, [Ra(base)+Ra(index)*8+offset]
174 | MACRO op, type, op1, [Ra(index)*4+offset]
176 | MACRO op, type, op1, [Ra(base)+Ra(index)*4+offset]
180 | MACRO op, type, op1, [Ra(index)*2+offset]
182 | MACRO op, type, op1, [Ra(base)+Ra(index)*2+offset]
187 | MACRO op, type, op1, [Ra(index)+offset]
189 | MACRO op, type, op1, [Ra(base)+Ra(index)+offset]
195 |.macro ASM_EXPAND_OP2_MEM_3, MACRO, op, type, op1, op2, op3
203 | MACRO op, type, op1, [offset], op3
205 | MACRO op, type, op1, [Ra(base)+offset], op3
209 | MACRO op, type, op1, [Ra(index)*8+offset], op3
211 | MACRO op, type, op1, [Ra(base)+Ra(index)*8+offset], op3
215 | MACRO op, type, op1, [Ra(index)*4+offset], op3
217 | MACRO op, type, op1, [Ra(base)+Ra(index)*4+offset], op3
221 | MACRO op, type, op1, [Ra(index)*2+offset], op3
223 | MACRO op, type, op1, [Ra(base)+Ra(index)*2+offset], op3
228 | MACRO op, type, op1, [Ra(index)+offset], op3
230 | MACRO op, type, op1, [Ra(base)+Ra(index)+offset], op3
236 |.macro ASM_EXPAND_OP3_MEM, MACRO, op, type, op1, op2, op3
244 | MACRO op, type, op1, op2, [offset]
246 | MACRO op, type, op1, op2, [Ra(base)+offset]
250 | MACRO op, type, op1, op2, [Ra(index)*8+offset]
252 | MACRO op, type, op1, op2, [Ra(base)+Ra(index)*8+offset]
256 | MACRO op, type, op1, op2, [Ra(index)*4+offset]
258 | MACRO op, type, op1, op2, [Ra(base)+Ra(index)*4+offset]
262 | MACRO op, type, op1, op2, [Ra(index)*2+offset]
264 | MACRO op, type, op1, op2, [Ra(base)+Ra(index)*2+offset]
269 | MACRO op, type, op1, op2, [Ra(index)+offset]
271 | MACRO op, type, op1, op2, [Ra(base)+Ra(index)+offset]
277 |.macro ASM_EXPAND_TYPE_MEM, op, type, op1
282 | op byte op1
285 | op word op1
288 | op dword op1
292 | op qword op1
298 |.macro ASM_EXPAND_TYPE_MEM_REG, op, type, op1, op2
303 | op byte op1, Rb(op2)
306 | op word op1, Rw(op2)
309 | op dword op1, Rd(op2)
313 | op qword op1, Rq(op2)
319 |.macro ASM_EXPAND_TYPE_MEM_TXT, op, type, op1, op2
324 | op byte op1, op2
327 | op word op1, op2
330 | op dword op1, op2
334 | op qword op1, op2
340 |.macro ASM_EXPAND_TYPE_MEM_IMM, op, type, op1, op2
345 | op byte op1, (op2 & 0xff)
348 | op word op1, (op2 & 0xffff)
351 | op dword op1, op2
355 | op qword op1, op2
361 |.macro ASM_EXPAND_TYPE_REG_MEM, op, type, op1, op2
366 | op Rb(op1), byte op2
369 | op Rw(op1), word op2
372 | op Rd(op1), dword op2
376 | op Rq(op1), qword op2
382 |.macro ASM_TMEM_OP, op, type, op1
384 || int32_t offset = IR_MEM_OFFSET(op1);
385 || int32_t base = IR_MEM_BASE(op1);
386 || int32_t index = IR_MEM_INDEX(op1);
387 || int32_t scale = IR_MEM_SCALE(op1);
423 |.macro ASM_TXT_TMEM_OP, op, op1, type, op2
431 | op op1, type [offset]
433 | op op1, type [Ra(base)+offset]
437 | op op1, type [Ra(index)*8+offset]
439 | op op1, type [Ra(base)+Ra(index)*8+offset]
443 | op op1, type [Ra(index)*4+offset]
445 | op op1, type [Ra(base)+Ra(index)*4+offset]
449 | op op1, type [Ra(index)*2+offset]
451 | op op1, type [Ra(base)+Ra(index)*2+offset]
456 | op op1, type [Ra(index)+offset]
458 | op op1, type [Ra(base)+Ra(index)+offset]
464 |.macro ASM_TMEM_TXT_OP, op, type, op1, op2
466 || int32_t offset = IR_MEM_OFFSET(op1);
467 || int32_t base = IR_MEM_BASE(op1);
468 || int32_t index = IR_MEM_INDEX(op1);
469 || int32_t scale = IR_MEM_SCALE(op1);
505 |.macro ASM_TXT_TXT_TMEM_OP, op, op1, op2, type, op3
513 | op op1, op2, type [offset]
515 | op op1, op2, type [Ra(base)+offset]
519 | op op1, op2, type [Ra(index)*8+offset]
521 | op op1, op2, type [Ra(base)+Ra(index)*8+offset]
525 | op op1, op2, type [Ra(index)*4+offset]
527 | op op1, op2, type [Ra(base)+Ra(index)*4+offset]
531 | op op1, op2, type [Ra(index)*2+offset]
533 | op op1, op2, type [Ra(base)+Ra(index)*2+offset]
538 | op op1, op2, type [Ra(index)+offset]
540 | op op1, op2, type [Ra(base)+Ra(index)+offset]
546 |.macro ASM_REG_OP, op, type, op1
551 | op Rb(op1)
554 | op Rw(op1)
557 | op Rd(op1)
561 | op Rq(op1)
567 |.macro ASM_MEM_OP, op, type, op1
568 | ASM_EXPAND_OP_MEM ASM_EXPAND_TYPE_MEM, op, type, op1
571 |.macro ASM_REG_REG_OP, op, type, op1, op2
576 | op Rb(op1), Rb(op2)
579 | op Rw(op1), Rw(op2)
582 | op Rd(op1), Rd(op2)
586 | op Rq(op1), Rq(op2)
592 |.macro ASM_REG_REG_OP2, op, type, op1, op2
598 | op Rw(op1), Rw(op2)
601 | op Rd(op1), Rd(op2)
605 | op Rq(op1), Rq(op2)
611 |.macro ASM_REG_TXT_OP, op, type, op1, op2
616 | op Rb(op1), op2
619 | op Rw(op1), op2
622 | op Rd(op1), op2
626 | op Rq(op1), op2
632 |.macro ASM_REG_IMM_OP, op, type, op1, op2
637 | op Rb(op1), (op2 & 0xff)
640 | op Rw(op1), (op2 & 0xffff)
643 | op Rd(op1), op2
647 | op Rq(op1), op2
653 |.macro ASM_MEM_REG_OP, op, type, op1, op2
654 | ASM_EXPAND_OP1_MEM ASM_EXPAND_TYPE_MEM_REG, op, type, op1, op2
657 |.macro ASM_MEM_TXT_OP, op, type, op1, op2
658 | ASM_EXPAND_OP1_MEM ASM_EXPAND_TYPE_MEM_TXT, op, type, op1, op2
661 |.macro ASM_MEM_IMM_OP, op, type, op1, op2
662 | ASM_EXPAND_OP1_MEM ASM_EXPAND_TYPE_MEM_IMM, op, type, op1, op2
665 |.macro ASM_REG_MEM_OP, op, type, op1, op2
666 | ASM_EXPAND_OP2_MEM ASM_REG_TXT_OP, op, type, op1, op2
669 |.macro ASM_REG_REG_MUL, op, type, op1, op2
674 | op Rw(op1), Rw(op2)
677 | op Rd(op1), Rd(op2)
681 | op Rq(op1), Rq(op2)
687 |.macro ASM_REG_IMM_MUL, op, type, op1, op2
692 | op Rw(op1), op2
695 | op Rd(op1), op2
699 | op Rq(op1), op2
705 |.macro ASM_REG_TXT_MUL, op, type, op1, op2
710 | op Rw(op1), op2
713 | op Rd(op1), op2
717 | op Rq(op1), op2
723 |.macro ASM_REG_MEM_MUL, op, type, op1, op2
724 | ASM_EXPAND_OP2_MEM ASM_REG_TXT_MUL, op, type, op1, op2
727 |.macro ASM_REG_TXT_TXT_MUL, op, type, op1, op2, op3
732 | op Rw(op1), op2, op3
735 | op Rd(op1), op2, op3
739 | op Rq(op1), op2, op3
745 |.macro ASM_REG_MEM_TXT_MUL, op, type, op1, op2, op3
746 | ASM_EXPAND_OP2_MEM_3 ASM_REG_TXT_TXT_MUL, imul, type, op1, op2, op3
749 |.macro ASM_SSE2_REG_REG_OP, op, type, op1, op2
751 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST)
754 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST)
758 |.macro ASM_SSE2_REG_TXT_OP, op, type, op1, op2
760 | op..d xmm(op1-IR_REG_FP_FIRST), qword op2
763 | op..s xmm(op1-IR_REG_FP_FIRST), dword op2
767 |.macro ASM_SSE2_REG_MEM_OP, op, type, op1, op2
768 | ASM_EXPAND_OP2_MEM ASM_SSE2_REG_TXT_OP, op, type, op1, op2
771 |.macro ASM_AVX_REG_REG_REG_OP, op, type, op1, op2, op3
773 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), xmm(op3-IR_REG_FP_FIRST)
776 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), xmm(op3-IR_REG_FP_FIRST)
780 |.macro ASM_AVX_REG_REG_TXT_OP, op, type, op1, op2, op3
782 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), qword op3
785 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), dword op3
789 |.macro ASM_AVX_REG_REG_MEM_OP, op, type, op1, op2, op3
790 | ASM_EXPAND_OP3_MEM ASM_AVX_REG_REG_TXT_OP, op, type, op1, op2, op3
793 |.macro ASM_FP_REG_REG_OP, op, type, op1, op2
795 | ASM_SSE2_REG_REG_OP v..op, type, op1, op2
797 | ASM_SSE2_REG_REG_OP op, type, op1, op2
818 |.macro ASM_FP_MEM_REG_OP, op, type, op1, op2
819 | ASM_EXPAND_OP1_MEM ASM_FP_TXT_REG_OP, op, type, op1, op2
822 |.macro ASM_FP_REG_TXT_OP, op, type, op1, op2
824 | ASM_SSE2_REG_TXT_OP v..op, type, op1, op2
826 | ASM_SSE2_REG_TXT_OP op, type, op1, op2
830 |.macro ASM_FP_REG_MEM_OP, op, type, op1, op2
832 | ASM_SSE2_REG_MEM_OP v..op, type, op1, op2
834 | ASM_SSE2_REG_MEM_OP op, type, op1, op2
838 |.macro ASM_SSE2_REG_REG_TXT_OP, op, type, op1, op2, op3
840 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), op3
843 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), op3
847 |.macro ASM_SSE2_REG_REG_REG_TXT_OP, op, type, op1, op2, op3, op4
849 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), xmm(op3-IR_REG_FP_FIRST), op4
852 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), xmm(op3-IR_REG_FP_FIRST), op4
856 |.macro ASM_FP_REG_REG_TXT_OP, op, type, op1, op2, op3
858 | ASM_SSE2_REG_REG_REG_TXT_OP v..op, type, op1, op2, op3
860 | ASM_SSE2_REG_REG_TXT_OP op, type, op1, op2, op3
1144 if (ctx->ir_base[insn->op1].op == IR_RLOAD) {
1152 if (IR_IS_CONST_REF(insn->op2) && insn->op1 != insn->op2) {
1207 if (IR_IS_CONST_REF(insn->op2) && insn->op1 != insn->op2) {
1216 if (IR_IS_CONST_REF(insn->op1)) {
1217 const ir_insn *val_insn = &ctx->ir_base[insn->op1];
1220 } else if (ir_rule(ctx, insn->op1) == IR_STATIC_ALLOCA) {
1223 } else if (ir_rule(ctx, insn->op1) & IR_FUSED) {
1226 if (IR_IS_CONST_REF(insn->op2) && insn->op1 != insn->op2) {
1241 if (IR_IS_CONST_REF(insn->op1)) {
1242 const ir_insn *val_insn = &ctx->ir_base[insn->op1];
1250 if (IR_IS_CONST_REF(insn->op1)) {
1257 if (!IR_IS_TYPE_INT(ctx->ir_base[insn->op1].type)) {
1435 if (IR_IS_CONST_REF(insn->op1)) {
1532 SWAP_REFS(insn->op1, insn->op2);
1540 if (insn->op1 == insn->op2) {
1545 } else if (ir_match_try_fuse_load(ctx, insn->op1, ref)) {
1594 if (insn->op1 == ref) {
1607 } else if (insn->op2 == ref && insn->op1 != insn->op2) {
1736 } else if (ir_match_try_fuse_load(ctx, insn->op1, root)) {
1745 && (IR_IS_CONST_REF(insn->op1) || ir_match_try_fuse_load(ctx, insn->op1, root))) {
1754 ir_match_fuse_load(ctx, insn->op1, root);
1756 && ir_match_try_fuse_load(ctx, insn->op1, root)) {
1768 ir_match_fuse_load(ctx, insn->op1, root);
1770 && ir_match_try_fuse_load(ctx, insn->op1, root)) {
1788 …else if ((IR_IS_CONST_REF(insn->op1) && !IR_IS_FP_ZERO(ctx->ir_base[insn->op1])) || ir_match_try_f…
1815 …else if ((IR_IS_CONST_REF(insn->op1) && !IR_IS_FP_ZERO(ctx->ir_base[insn->op1])) || ir_match_try_f…
1909 if (IR_IS_TYPE_INT(ctx->ir_base[insn->op1].type)) {
1913 && insn->op1 == ref - 1) { /* previous instruction */
1914 ir_insn *op1_insn = &ctx->ir_base[insn->op1];
1916 if (op1_insn->op == IR_AND && ctx->use_lists[insn->op1].count == 1) {
1919 ctx->rules[insn->op1] = IR_FUSED | IR_TEST_INT;
1928 ctx->rules[insn->op1] = IR_BINOP_INT | IR_MAY_SWAP;
1931 ctx->rules[insn->op1] = IR_BINOP_INT;
1948 if (IR_IS_CONST_REF(insn->op1)) {
1961 if (ctx->use_lists[insn->op1].count == 1 || ir_match_fuse_addr_all_useges(ctx, insn->op1)) {
1962 uint32_t rule = ctx->rules[insn->op1];
1965 ctx->rules[insn->op1] = rule = ir_match_insn(ctx, insn->op1);
1969 ctx->rules[insn->op1] = IR_FUSED | IR_SIMPLE | IR_LEA_SI;
1973 ctx->rules[insn->op1] = IR_FUSED | IR_SIMPLE | IR_LEA_SIB;
1977 ctx->rules[insn->op1] = IR_FUSED | IR_SIMPLE | IR_LEA_IB;
2003 if (insn->op1 != insn->op2) {
2004 if (ctx->use_lists[insn->op1].count == 1 || ir_match_fuse_addr_all_useges(ctx, insn->op1)) {
2005 uint32_t rule =ctx->rules[insn->op1];
2007 ctx->rules[insn->op1] = rule = ir_match_insn(ctx, insn->op1);
2010 ctx->rules[insn->op1] = IR_FUSED | IR_SIMPLE | IR_LEA_OB;
2025 ctx->rules[insn->op1] = IR_FUSED | IR_SIMPLE | IR_LEA_SI;
2093 } else if (IR_IS_CONST_REF(insn->op1)) {
2113 && !IR_IS_CONST_REF(insn->op1)) {
2115 ir_match_fuse_load(ctx, insn->op1, ref);
2141 && !IR_IS_CONST_REF(insn->op1)) {
2143 ir_match_fuse_load(ctx, insn->op1, ref);
2157 } else if (IR_IS_CONST_REF(insn->op1)) {
2181 } else if (IR_IS_CONST_REF(insn->op1)) {
2197 IR_ASSERT(IR_IS_TYPE_INT(ctx->ir_base[insn->op1].type)); // TODO: IR_BOOL_NOT_FP
2221 } else if (IR_IS_CONST_REF(insn->op1)) {
2235 } else if (IR_IS_CONST_REF(insn->op1)) {
2249 } else if (IR_IS_CONST_REF(insn->op1)) {
2260 } else if (IR_IS_CONST_REF(insn->op1)) {
2266 // lea [op1*2]
2268 // lea [op1*4]
2270 // lea [op1*8]
2286 } else if (IR_IS_CONST_REF(insn->op1)) {
2369 if (insn->op1 == op_insn->op1
2370 && ctx->ir_base[op_insn->op1].op == load_op
2371 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2372 && ctx->use_lists[op_insn->op1].count == 2) {
2375 ctx->rules[op_insn->op1] = IR_SKIPPED | load_op;
2382 && insn->op1 == op_insn->op2
2389 ctx->rules[op_insn->op1] = IR_SKIPPED | load_op;
2393 if (insn->op1 == op_insn->op1
2394 && ctx->ir_base[op_insn->op1].op == load_op
2395 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2396 && ctx->use_lists[op_insn->op1].count == 2) {
2399 ctx->rules[op_insn->op1] = IR_SKIPPED | load_op;
2403 if (insn->op1 == op_insn->op1
2404 && ctx->ir_base[op_insn->op1].op == load_op
2405 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2406 && ctx->use_lists[op_insn->op1].count == 2){
2409 ctx->rules[op_insn->op1] = IR_SKIPPED | load_op;
2413 if (insn->op1 == op_insn->op1
2414 && ctx->ir_base[op_insn->op1].op == load_op
2415 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2416 && ctx->use_lists[op_insn->op1].count == 2) {
2419 ctx->rules[op_insn->op1] = IR_SKIPPED | load_op;
2423 if (insn->op1 == op_insn->op1
2424 && ctx->ir_base[op_insn->op1].op == load_op
2425 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2426 && ctx->use_lists[op_insn->op1].count == 2) {
2429 ctx->rules[op_insn->op1] = IR_SKIPPED | load_op;
2433 if (insn->op1 == op_insn->op1
2434 && ctx->ir_base[op_insn->op1].op == load_op
2435 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2436 && ctx->use_lists[op_insn->op1].count == 2) {
2439 ctx->rules[op_insn->op1] = IR_SKIPPED | load_op;
2443 if (insn->op1 == op_insn->op1
2444 && ctx->ir_base[op_insn->op1].op == load_op
2445 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2446 && ctx->use_lists[op_insn->op1].count == 2) {
2449 ctx->rules[op_insn->op1] = IR_SKIPPED | load_op;
2453 if (insn->op1 == op_insn->op1
2454 && ctx->ir_base[op_insn->op1].op == load_op
2455 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2456 && ctx->use_lists[op_insn->op1].count == 2) {
2459 ctx->rules[op_insn->op1] = IR_SKIPPED | load_op;
2463 if (insn->op1 == op_insn->op1
2464 && ctx->ir_base[op_insn->op1].op == load_op
2465 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2466 && ctx->use_lists[op_insn->op1].count == 2) {
2469 ctx->rules[op_insn->op1] = IR_SKIPPED | load_op;
2520 if (insn->op1 == op_insn->op1
2521 && ctx->ir_base[op_insn->op1].op == IR_RLOAD
2522 && ctx->ir_base[op_insn->op1].op2 == insn->op3
2523 && ctx->use_lists[op_insn->op1].count == 2) {
2526 ctx->rules[op_insn->op1] = IR_SKIPPED | IR_RLOAD;
2529 && insn->op1 == op_insn->op2
2536 ctx->rules[op_insn->op1] = IR_SKIPPED | IR_RLOAD;
2566 if (IR_IS_TYPE_INT(ctx->ir_base[op2_insn->op1].type)) {
2570 && op2_insn->op1 == insn->op2 - 1) { /* previous instruction */
2571 ir_insn *op1_insn = &ctx->ir_base[op2_insn->op1];
2573 if (op1_insn->op == IR_AND && ctx->use_lists[op2_insn->op1].count == 1) {
2576 ctx->rules[op2_insn->op1] = IR_FUSED | IR_TEST_INT;
2587 ctx->rules[op2_insn->op1] = IR_BINOP_INT | IR_MAY_SWAP;
2590 ctx->rules[op2_insn->op1] = IR_BINOP_INT;
2638 && insn->op1 == ref - 1 /* previous instruction */
2642 ir_insn *store_insn = &ctx->ir_base[insn->op1];
2653 if (ctx->ir_base[op_insn->op1].op == IR_LOAD
2654 && ctx->ir_base[op_insn->op1].op2 == store_insn->op2) {
2655 if (ir_in_same_block(ctx, op_insn->op1)
2656 && ctx->use_lists[op_insn->op1].count == 2
2657 && store_insn->op1 == op_insn->op1) {
2660 ctx->rules[op_insn->op1] = IR_SKIPPED | IR_LOAD;
2662 ctx->rules[insn->op1] = IR_MEM_BINOP_INT;
2670 && store_insn->op1 == op_insn->op2) {
2674 ctx->rules[op_insn->op1] = IR_SKIPPED | IR_LOAD;
2676 ctx->rules[insn->op1] = IR_MEM_BINOP_INT;
2690 if (!IR_IS_CONST_REF(insn->op1) && ctx->use_lists[insn->op1].count == 1) {
2691 ir_insn *op1_insn = &ctx->ir_base[insn->op1];
2694 if (IR_IS_TYPE_INT(ctx->ir_base[op1_insn->op1].type)) {
2696 ctx->rules[insn->op1] = IR_FUSED | IR_CMP_INT;
2700 ctx->rules[insn->op1] = IR_FUSED | IR_CMP_FP;
2715 if (IR_IS_TYPE_INT(ctx->ir_base[op2_insn->op1].type)) {
2719 if (op2_insn->op1 == insn->op2 - 1) { /* previous instruction */
2720 ir_insn *op1_insn = &ctx->ir_base[op2_insn->op1];
2728 ctx->rules[op2_insn->op1] = IR_BINOP_INT | IR_MAY_SWAP;
2731 ctx->rules[op2_insn->op1] = IR_BINOP_INT;
2738 && op2_insn->op1 == insn->op2 - 2 /* before previous instruction */
2739 && ir_in_same_block(ctx, op2_insn->op1)
2740 && ctx->use_lists[op2_insn->op1].count == 2) {
2743 if (store_insn->op == IR_STORE && store_insn->op3 == op2_insn->op1) {
2744 ir_insn *op_insn = &ctx->ir_base[op2_insn->op1];
2750 if (ctx->ir_base[op_insn->op1].op == IR_LOAD
2751 && ctx->ir_base[op_insn->op1].op2 == store_insn->op2) {
2752 if (ir_in_same_block(ctx, op_insn->op1)
2753 && ctx->use_lists[op_insn->op1].count == 2
2754 && store_insn->op1 == op_insn->op1) {
2756 ctx->rules[op2_insn->op1] = IR_FUSED | IR_BINOP_INT;
2757 ctx->rules[op_insn->op1] = IR_SKIPPED | IR_LOAD;
2768 && store_insn->op1 == op_insn->op2) {
2771 ctx->rules[op2_insn->op1] = IR_FUSED | IR_BINOP_INT;
2772 ctx->rules[op_insn->op1] = IR_SKIPPED | IR_LOAD;
2807 …if (ir_type_size[ctx->ir_base[insn->op1].type] > (IR_IS_TYPE_SIGNED(ctx->ir_base[insn->op1].type) …
2808 ir_match_fuse_load(ctx, insn->op1, ref);
2815 ir_match_fuse_load(ctx, insn->op1, ref);
2819 ir_match_fuse_load(ctx, insn->op1, ref);
2822 ir_match_fuse_load(ctx, insn->op1, ref);
2823 if (IR_IS_TYPE_INT(insn->type) && IR_IS_TYPE_INT(ctx->ir_base[insn->op1].type)) {
2830 ir_match_fuse_load(ctx, insn->op1, ref);
2833 ir_match_fuse_load(ctx, insn->op1, ref);
3272 if (ir_rule(ctx, insn->op1) == IR_STATIC_ALLOCA) {
3273 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op1].op3);
3294 if (ir_rule(ctx, insn->op1) == IR_STATIC_ALLOCA) {
3295 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op1].op3);
3312 op1_insn = &ctx->ir_base[insn->op1];
3319 index_reg_ref = insn->op1 * sizeof(ir_ref) + 1;
3320 } else if (ir_rule(ctx, op1_insn->op1) == IR_STATIC_ALLOCA) {
3321 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[op1_insn->op1].op3);
3326 base_reg_ref = insn->op1 * sizeof(ir_ref) + 1;
3334 if (ir_rule(ctx, insn->op1) == IR_STATIC_ALLOCA) {
3335 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op1].op3);
3339 } else if (ir_rule(ctx, op2_insn->op1) == IR_STATIC_ALLOCA) {
3340 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[op2_insn->op1].op3);
3350 index_reg_ref = insn->op1 * sizeof(ir_ref) + 1;
3351 op1_insn = &ctx->ir_base[insn->op1];
3357 base_reg_ref = index_reg_ref = insn->op1 * sizeof(ir_ref) + 1;
3358 op1_insn = &ctx->ir_base[insn->op1];
3363 base_reg_ref = insn->op1 * sizeof(ir_ref) + 1;
3364 index_reg_ref = insn->op1 * sizeof(ir_ref) + 2;
3370 op1_insn = &ctx->ir_base[insn->op1];
3374 if (ir_rule(ctx, op1_insn->op1) == IR_STATIC_ALLOCA) {
3375 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[op1_insn->op1].op3);
3379 base_reg_ref = insn->op1 * sizeof(ir_ref) + 1;
3383 index_reg_ref = insn->op1 * sizeof(ir_ref) + 1;
3384 op1_insn = &ctx->ir_base[insn->op1];
3388 if (ir_rule(ctx, op2_insn->op1) == IR_STATIC_ALLOCA) {
3389 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[op2_insn->op1].op3);
3397 if (ir_rule(ctx, insn->op1) == IR_STATIC_ALLOCA) {
3398 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op1].op3);
3410 index_reg_ref = insn->op1 * sizeof(ir_ref) + 1;
3418 op1_insn = &ctx->ir_base[insn->op1];
3753 ir_ref op1 = insn->op1;
3763 ir_emit_load(ctx, type, op1_reg, op1);
3769 ir_emit_load(ctx, type, def_reg, op1);
3771 if (op1 == op2) {
3779 if (op1 != op2) {
3880 ir_ref op1 = insn->op1;
3887 IR_ASSERT(!IR_IS_CONST_REF(op1));
3892 ir_emit_load(ctx, type, op1_reg, op1);
3912 if (ir_rule(ctx, op1) & IR_FUSED) {
3913 mem = ir_fuse_load(ctx, def, op1);
3915 mem = ir_ref_spill_slot(ctx, op1);
3929 ir_ref op1 = insn->op1;
3939 ir_emit_load(ctx, type, op1_reg, op1);
3945 ir_emit_load(ctx, type, def_reg, op1);
3951 if (op1 != op2) {
3956 if (op1 == op2) {
3986 ir_type type = ctx->ir_base[insn->op1].type;
4005 ir_type type = ctx->ir_base[overflow_insn->op1].type;
4173 ir_ref op1 = insn->op1;
4183 ir_emit_load(ctx, type, op1_reg, op1);
4189 ir_emit_load(ctx, type, def_reg, op1);
4232 ir_ref op1 = insn->op1;
4245 ir_emit_load(ctx, type, op1_reg, op1);
4295 ir_ref op1 = insn->op1;
4309 ir_emit_load(ctx, type, op1_reg, op1);
4315 ir_emit_load(ctx, type, def_reg, op1);
4396 ir_emit_load(ctx, type, op1_reg, insn->op1);
4417 ir_emit_load(ctx, type, def_reg, insn->op1);
4499 ir_ref op1 = insn->op1;
4510 ir_emit_load(ctx, type, op1_reg, op1);
4516 ir_emit_load(ctx, type, def_reg, op1);
4589 ir_ref op1 = insn->op1;
4597 ir_emit_load(ctx, type, op1_reg, op1);
4603 ir_emit_load(ctx, type, def_reg, op1);
4640 ir_ref op1 = insn->op1;
4649 ir_emit_load(ctx, type, op1_reg, op1);
4730 if (ir_rule(ctx, op1) & IR_FUSED) {
4731 mem = ir_fuse_load(ctx, def, op1);
4733 mem = ir_ref_spill_slot(ctx, op1);
4807 ir_ref op1 = insn->op1;
4817 ir_emit_load(ctx, type, def_reg, op1);
4826 ir_emit_load(ctx, type, op1_reg, op1);
4964 ir_ref op1 = insn->op1;
4972 ir_emit_load(ctx, type, op1_reg, op1);
4989 ir_type type = ctx->ir_base[insn->op1].type;
4990 ir_ref op1 = insn->op1;
4998 ir_emit_load(ctx, type, op1_reg, op1);
5004 ir_mem mem = ir_ref_spill_slot(ctx, op1);
5020 ir_ref op1 = insn->op1;
5029 ir_emit_load(ctx, type, op1_reg, op1);
5035 ir_emit_load(ctx, type, IR_REG_RAX, op1);
5038 if (op2_reg == IR_REG_NONE && op1 == op2) {
5175 ir_ref op1 = insn->op1;
5183 ir_emit_load(ctx, type, op1_reg, op1);
5189 ir_emit_load(ctx, type, def_reg, op1);
5266 ir_ref op1 = insn->op1;
5276 ir_emit_load(ctx, type, op1_reg, op1);
5282 ir_emit_load(ctx, type, def_reg, op1);
5284 if (op1 == op2) {
5291 if (op1 != op2) {
5383 ir_ref op1 = insn->op1;
5393 ir_emit_load(ctx, type, op1_reg, op1);
5398 if (op1 != op2) {
5485 …ctx *ctx, ir_type type, ir_ref root, ir_insn *insn, ir_reg op1_reg, ir_ref op1, ir_reg op2_reg, ir…
5508 } else if (IR_IS_CONST_REF(op1)) {
5513 if (ir_rule(ctx, op1) & IR_FUSED) {
5514 mem = ir_fuse_load(ctx, root, op1);
5516 mem = ir_ref_spill_slot(ctx, op1);
5529 ir_type type = ctx->ir_base[cmp_insn->op1].type;
5530 ir_ref op1 = cmp_insn->op1;
5537 ir_emit_load(ctx, type, op1_reg, op1);
5541 if (op1 != op2) {
5546 ir_emit_cmp_int_common(ctx, type, root, cmp_insn, op1_reg, op1, op2_reg, op2);
5636 ir_type type = ctx->ir_base[insn->op1].type;
5638 ir_ref op1 = insn->op1;
5647 ir_emit_load(ctx, type, op1_reg, op1);
5651 if (op1 != op2) {
5676 ir_emit_cmp_int_common(ctx, type, def, insn, op1_reg, op1, op2_reg, op2);
5689 ir_ref op1 = binop_insn->op1;
5698 ir_emit_load(ctx, type, op1_reg, op1);
5703 if (op1 != op2) {
5742 } else if (IR_IS_CONST_REF(op1)) {
5747 if (ir_rule(ctx, op1) & IR_FUSED) {
5748 mem = ir_fuse_load(ctx, root, op1);
5750 mem = ir_ref_spill_slot(ctx, op1);
5755 if (op1 != op2) {
5761 IR_ASSERT(!IR_IS_CONST_REF(op1));
5773 ir_emit_test_int_common(ctx, def, insn->op1, insn->op);
5795 ir_type type = ctx->ir_base[cmp_insn->op1].type;
5797 ir_ref op1, op2;
5800 op1 = cmp_insn->op1;
5808 SWAP_REFS(op1, op2);
5818 ir_emit_load(ctx, type, op1_reg, op1);
5823 if (op1 != op2) {
6053 ir_type type = ctx->ir_base[cmp_insn->op1].type;
6054 ir_ref op1 = cmp_insn->op1;
6061 ir_emit_load(ctx, type, op1_reg, op1);
6065 if (op1 != op2) {
6086 ir_insn *prev_insn = &ctx->ir_base[insn->op1];
6088 if (ir_rule(ctx, prev_insn->op1) == IR_CMP_AND_BRANCH_INT) {
6089 prev_insn = &ctx->ir_base[prev_insn->op1];
6091 if (prev_insn->op1 == cmp_insn->op1 && prev_insn->op2 == cmp_insn->op2) {
6097 ir_emit_cmp_int_common(ctx, type, def, cmp_insn, op1_reg, op1, op2_reg, op2);
6108 op2 = ctx->ir_base[op2].op1;
6177 ir_ref op1 = insn->op1;
6180 ir_type op1_type = ctx->ir_base[op1].type;
6191 if (op1 == op2) {
6201 if (op1 == op2) {
6205 if (op1_reg != IR_REG_NONE && op1 != op2 && op1 != op3 && IR_REG_SPILLED(op1_reg)) {
6207 ir_emit_load(ctx, op1_type, op1_reg, op1);
6214 ir_mem mem = ir_ref_spill_slot(ctx, op1);
6328 ir_emit_cmp_int_common2(ctx, def, insn->op1, &ctx->ir_base[insn->op1]);
6329 op = ctx->ir_base[insn->op1].op;
6492 op = ir_emit_cmp_fp_common(ctx, def, insn->op1, &ctx->ir_base[insn->op1]);
6649 ir_type src_type = ctx->ir_base[insn->op1].type;
6663 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
6695 } else if (IR_IS_CONST_REF(insn->op1)) {
6700 if (ir_rule(ctx, insn->op1) & IR_FUSED) {
6701 mem = ir_fuse_load(ctx, def, insn->op1);
6703 mem = ir_ref_spill_slot(ctx, insn->op1);
6745 ir_type src_type = ctx->ir_base[insn->op1].type;
6759 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
6794 } else if (IR_IS_CONST_REF(insn->op1)) {
6799 if (ir_rule(ctx, insn->op1) & IR_FUSED) {
6800 mem = ir_fuse_load(ctx, def, insn->op1);
6802 mem = ir_ref_spill_slot(ctx, insn->op1);
6843 ir_type src_type = ctx->ir_base[insn->op1].type;
6854 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
6860 ir_emit_load_ex(ctx, dst_type, def_reg, insn->op1, def);
6870 ir_type src_type = ctx->ir_base[insn->op1].type;
6882 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
6888 ir_emit_load_ex(ctx, dst_type, def_reg, insn->op1, def);
6894 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
6900 ir_emit_load_ex(ctx, dst_type, def_reg, insn->op1, def);
6907 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
6926 } else if (IR_IS_CONST_REF(insn->op1)) {
6927 ir_insn *_insn = &ctx->ir_base[insn->op1];
6941 if (ir_rule(ctx, insn->op1) & IR_FUSED) {
6942 mem = ir_fuse_load(ctx, def, insn->op1);
6944 mem = ir_ref_spill_slot(ctx, insn->op1);
6962 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
6981 } else if (IR_IS_CONST_REF(insn->op1)) {
6982 int label = ir_const_label(ctx, insn->op1);
6988 if (ir_rule(ctx, insn->op1) & IR_FUSED) {
6989 mem = ir_fuse_load(ctx, def, insn->op1);
6991 mem = ir_ref_spill_slot(ctx, insn->op1);
7005 ir_type src_type = ctx->ir_base[insn->op1].type;
7019 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
7107 if (ir_rule(ctx, insn->op1) & IR_FUSED) {
7108 mem = ir_fuse_load(ctx, def, insn->op1);
7110 mem = ir_ref_spill_slot(ctx, insn->op1);
7164 ir_type src_type = ctx->ir_base[insn->op1].type;
7181 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
7217 } else if (IR_IS_CONST_REF(insn->op1)) {
7218 int label = ir_const_label(ctx, insn->op1);
7257 if (ir_rule(ctx, insn->op1) & IR_FUSED) {
7258 mem = ir_fuse_load(ctx, def, insn->op1);
7260 mem = ir_ref_spill_slot(ctx, insn->op1);
7306 ir_type src_type = ctx->ir_base[insn->op1].type;
7318 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
7338 } else if (IR_IS_CONST_REF(insn->op1)) {
7339 int label = ir_const_label(ctx, insn->op1);
7358 if (ir_rule(ctx, insn->op1) & IR_FUSED) {
7359 mem = ir_fuse_load(ctx, def, insn->op1);
7361 mem = ir_ref_spill_slot(ctx, insn->op1);
7393 ir_emit_load(ctx, type, op1_reg, insn->op1);
7400 ir_emit_load(ctx, type, def_reg, insn->op1);
7420 ir_emit_load(ctx, type, op1_reg, insn->op1);
7427 ir_emit_load(ctx, type, def_reg, insn->op1);
7449 mem = ir_var_spill_slot(ctx, insn->op1);
7668 ir_type type = ctx->ir_base[cmp_insn->op1].type;
7669 ir_ref op1 = cmp_insn->op1;
7690 ir_emit_load(ctx, type, op1_reg, op1);
7694 if (op1 != op2) {
7699 ir_emit_cmp_int_common(ctx, type, ref, cmp_insn, op1_reg, op1, op2_reg, op2);
9316 ir_type type = ctx->ir_base[cmp_insn->op1].type;
9317 ir_ref op1 = cmp_insn->op1;
9325 ir_emit_load(ctx, type, op1_reg, op1);
9329 if (op1 != op2) {
9360 ir_emit_cmp_int_common(ctx, type, def, cmp_insn, op1_reg, op1, op2_reg, op2);
9407 type = ctx->ir_base[ctx->ir_base[insn->op2].op1].type;
10098 } else if (j > 1 && input == insn->op1 && ctx->regs[i][1] != IR_REG_NONE) {
