Lines Matching refs:op1
72 |.macro ASM_EXPAND_OP_MEM, MACRO, op, type, op1
74 || int32_t offset = IR_MEM_OFFSET(op1);
75 || int32_t base = IR_MEM_BASE(op1);
76 || int32_t index = IR_MEM_INDEX(op1);
77 || int32_t scale = IR_MEM_SCALE(op1);
113 |.macro ASM_EXPAND_OP1_MEM, MACRO, op, type, op1, op2
115 || int32_t offset = IR_MEM_OFFSET(op1);
116 || int32_t base = IR_MEM_BASE(op1);
117 || int32_t index = IR_MEM_INDEX(op1);
118 || int32_t scale = IR_MEM_SCALE(op1);
154 |.macro ASM_EXPAND_OP2_MEM, MACRO, op, type, op1, op2
162 | MACRO op, type, op1, [offset]
164 | MACRO op, type, op1, [Ra(base)+offset]
168 | MACRO op, type, op1, [Ra(index)*8+offset]
170 | MACRO op, type, op1, [Ra(base)+Ra(index)*8+offset]
174 | MACRO op, type, op1, [Ra(index)*4+offset]
176 | MACRO op, type, op1, [Ra(base)+Ra(index)*4+offset]
180 | MACRO op, type, op1, [Ra(index)*2+offset]
182 | MACRO op, type, op1, [Ra(base)+Ra(index)*2+offset]
187 | MACRO op, type, op1, [Ra(index)+offset]
189 | MACRO op, type, op1, [Ra(base)+Ra(index)+offset]
195 |.macro ASM_EXPAND_OP2_MEM_3, MACRO, op, type, op1, op2, op3
203 | MACRO op, type, op1, [offset], op3
205 | MACRO op, type, op1, [Ra(base)+offset], op3
209 | MACRO op, type, op1, [Ra(index)*8+offset], op3
211 | MACRO op, type, op1, [Ra(base)+Ra(index)*8+offset], op3
215 | MACRO op, type, op1, [Ra(index)*4+offset], op3
217 | MACRO op, type, op1, [Ra(base)+Ra(index)*4+offset], op3
221 | MACRO op, type, op1, [Ra(index)*2+offset], op3
223 | MACRO op, type, op1, [Ra(base)+Ra(index)*2+offset], op3
228 | MACRO op, type, op1, [Ra(index)+offset], op3
230 | MACRO op, type, op1, [Ra(base)+Ra(index)+offset], op3
236 |.macro ASM_EXPAND_OP3_MEM, MACRO, op, type, op1, op2, op3
244 | MACRO op, type, op1, op2, [offset]
246 | MACRO op, type, op1, op2, [Ra(base)+offset]
250 | MACRO op, type, op1, op2, [Ra(index)*8+offset]
252 | MACRO op, type, op1, op2, [Ra(base)+Ra(index)*8+offset]
256 | MACRO op, type, op1, op2, [Ra(index)*4+offset]
258 | MACRO op, type, op1, op2, [Ra(base)+Ra(index)*4+offset]
262 | MACRO op, type, op1, op2, [Ra(index)*2+offset]
264 | MACRO op, type, op1, op2, [Ra(base)+Ra(index)*2+offset]
269 | MACRO op, type, op1, op2, [Ra(index)+offset]
271 | MACRO op, type, op1, op2, [Ra(base)+Ra(index)+offset]
277 |.macro ASM_EXPAND_TYPE_MEM, op, type, op1
282 | op byte op1
285 | op word op1
288 | op dword op1
292 | op qword op1
298 |.macro ASM_EXPAND_TYPE_MEM_REG, op, type, op1, op2
303 | op byte op1, Rb(op2)
306 | op word op1, Rw(op2)
309 | op dword op1, Rd(op2)
313 | op qword op1, Rq(op2)
319 |.macro ASM_EXPAND_TYPE_MEM_TXT, op, type, op1, op2
324 | op byte op1, op2
327 | op word op1, op2
330 | op dword op1, op2
334 | op qword op1, op2
340 |.macro ASM_EXPAND_TYPE_MEM_IMM, op, type, op1, op2
345 | op byte op1, (op2 & 0xff)
348 | op word op1, (op2 & 0xffff)
351 | op dword op1, op2
355 | op qword op1, op2
361 |.macro ASM_EXPAND_TYPE_REG_MEM, op, type, op1, op2
366 | op Rb(op1), byte op2
369 | op Rw(op1), word op2
372 | op Rd(op1), dword op2
376 | op Rq(op1), qword op2
382 |.macro ASM_TMEM_OP, op, type, op1
384 || int32_t offset = IR_MEM_OFFSET(op1);
385 || int32_t base = IR_MEM_BASE(op1);
386 || int32_t index = IR_MEM_INDEX(op1);
387 || int32_t scale = IR_MEM_SCALE(op1);
423 |.macro ASM_TXT_TMEM_OP, op, op1, type, op2
431 | op op1, type [offset]
433 | op op1, type [Ra(base)+offset]
437 | op op1, type [Ra(index)*8+offset]
439 | op op1, type [Ra(base)+Ra(index)*8+offset]
443 | op op1, type [Ra(index)*4+offset]
445 | op op1, type [Ra(base)+Ra(index)*4+offset]
449 | op op1, type [Ra(index)*2+offset]
451 | op op1, type [Ra(base)+Ra(index)*2+offset]
456 | op op1, type [Ra(index)+offset]
458 | op op1, type [Ra(base)+Ra(index)+offset]
464 |.macro ASM_TMEM_TXT_OP, op, type, op1, op2
466 || int32_t offset = IR_MEM_OFFSET(op1);
467 || int32_t base = IR_MEM_BASE(op1);
468 || int32_t index = IR_MEM_INDEX(op1);
469 || int32_t scale = IR_MEM_SCALE(op1);
505 |.macro ASM_TXT_TXT_TMEM_OP, op, op1, op2, type, op3
513 | op op1, op2, type [offset]
515 | op op1, op2, type [Ra(base)+offset]
519 | op op1, op2, type [Ra(index)*8+offset]
521 | op op1, op2, type [Ra(base)+Ra(index)*8+offset]
525 | op op1, op2, type [Ra(index)*4+offset]
527 | op op1, op2, type [Ra(base)+Ra(index)*4+offset]
531 | op op1, op2, type [Ra(index)*2+offset]
533 | op op1, op2, type [Ra(base)+Ra(index)*2+offset]
538 | op op1, op2, type [Ra(index)+offset]
540 | op op1, op2, type [Ra(base)+Ra(index)+offset]
546 |.macro ASM_REG_OP, op, type, op1
551 | op Rb(op1)
554 | op Rw(op1)
557 | op Rd(op1)
561 | op Rq(op1)
567 |.macro ASM_MEM_OP, op, type, op1
568 | ASM_EXPAND_OP_MEM ASM_EXPAND_TYPE_MEM, op, type, op1
571 |.macro ASM_REG_REG_OP, op, type, op1, op2
576 | op Rb(op1), Rb(op2)
579 | op Rw(op1), Rw(op2)
582 | op Rd(op1), Rd(op2)
586 | op Rq(op1), Rq(op2)
592 |.macro ASM_REG_REG_OP2, op, type, op1, op2
598 | op Rw(op1), Rw(op2)
601 | op Rd(op1), Rd(op2)
605 | op Rq(op1), Rq(op2)
611 |.macro ASM_REG_TXT_OP, op, type, op1, op2
616 | op Rb(op1), op2
619 | op Rw(op1), op2
622 | op Rd(op1), op2
626 | op Rq(op1), op2
632 |.macro ASM_REG_IMM_OP, op, type, op1, op2
637 | op Rb(op1), (op2 & 0xff)
640 | op Rw(op1), (op2 & 0xffff)
643 | op Rd(op1), op2
647 | op Rq(op1), op2
653 |.macro ASM_MEM_REG_OP, op, type, op1, op2
654 | ASM_EXPAND_OP1_MEM ASM_EXPAND_TYPE_MEM_REG, op, type, op1, op2
657 |.macro ASM_MEM_TXT_OP, op, type, op1, op2
658 | ASM_EXPAND_OP1_MEM ASM_EXPAND_TYPE_MEM_TXT, op, type, op1, op2
661 |.macro ASM_MEM_IMM_OP, op, type, op1, op2
662 | ASM_EXPAND_OP1_MEM ASM_EXPAND_TYPE_MEM_IMM, op, type, op1, op2
665 |.macro ASM_REG_MEM_OP, op, type, op1, op2
666 | ASM_EXPAND_OP2_MEM ASM_REG_TXT_OP, op, type, op1, op2
669 |.macro ASM_REG_REG_MUL, op, type, op1, op2
674 | op Rw(op1), Rw(op2)
677 | op Rd(op1), Rd(op2)
681 | op Rq(op1), Rq(op2)
687 |.macro ASM_REG_IMM_MUL, op, type, op1, op2
692 | op Rw(op1), op2
695 | op Rd(op1), op2
699 | op Rq(op1), op2
705 |.macro ASM_REG_TXT_MUL, op, type, op1, op2
710 | op Rw(op1), op2
713 | op Rd(op1), op2
717 | op Rq(op1), op2
723 |.macro ASM_REG_MEM_MUL, op, type, op1, op2
724 | ASM_EXPAND_OP2_MEM ASM_REG_TXT_MUL, op, type, op1, op2
727 |.macro ASM_REG_TXT_TXT_MUL, op, type, op1, op2, op3
732 | op Rw(op1), op2, op3
735 | op Rd(op1), op2, op3
739 | op Rq(op1), op2, op3
745 |.macro ASM_REG_MEM_TXT_MUL, op, type, op1, op2, op3
746 | ASM_EXPAND_OP2_MEM_3 ASM_REG_TXT_TXT_MUL, imul, type, op1, op2, op3
749 |.macro ASM_SSE2_REG_REG_OP, op, type, op1, op2
751 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST)
754 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST)
758 |.macro ASM_SSE2_REG_TXT_OP, op, type, op1, op2
760 | op..d xmm(op1-IR_REG_FP_FIRST), qword op2
763 | op..s xmm(op1-IR_REG_FP_FIRST), dword op2
767 |.macro ASM_SSE2_REG_MEM_OP, op, type, op1, op2
768 | ASM_EXPAND_OP2_MEM ASM_SSE2_REG_TXT_OP, op, type, op1, op2
771 |.macro ASM_AVX_REG_REG_REG_OP, op, type, op1, op2, op3
773 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), xmm(op3-IR_REG_FP_FIRST)
776 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), xmm(op3-IR_REG_FP_FIRST)
780 |.macro ASM_AVX_REG_REG_TXT_OP, op, type, op1, op2, op3
782 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), qword op3
785 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), dword op3
789 |.macro ASM_AVX_REG_REG_MEM_OP, op, type, op1, op2, op3
790 | ASM_EXPAND_OP3_MEM ASM_AVX_REG_REG_TXT_OP, op, type, op1, op2, op3
793 |.macro ASM_FP_REG_REG_OP, op, type, op1, op2
795 | ASM_SSE2_REG_REG_OP v..op, type, op1, op2
797 | ASM_SSE2_REG_REG_OP op, type, op1, op2
818 |.macro ASM_FP_MEM_REG_OP, op, type, op1, op2
819 | ASM_EXPAND_OP1_MEM ASM_FP_TXT_REG_OP, op, type, op1, op2
822 |.macro ASM_FP_REG_TXT_OP, op, type, op1, op2
824 | ASM_SSE2_REG_TXT_OP v..op, type, op1, op2
826 | ASM_SSE2_REG_TXT_OP op, type, op1, op2
830 |.macro ASM_FP_REG_MEM_OP, op, type, op1, op2
832 | ASM_SSE2_REG_MEM_OP v..op, type, op1, op2
834 | ASM_SSE2_REG_MEM_OP op, type, op1, op2
838 |.macro ASM_SSE2_REG_REG_TXT_OP, op, type, op1, op2, op3
840 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), op3
843 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), op3
847 |.macro ASM_SSE2_REG_REG_REG_TXT_OP, op, type, op1, op2, op3, op4
849 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), xmm(op3-IR_REG_FP_FIRST), op4
852 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), xmm(op3-IR_REG_FP_FIRST), op4
856 |.macro ASM_FP_REG_REG_TXT_OP, op, type, op1, op2, op3
858 | ASM_SSE2_REG_REG_REG_TXT_OP v..op, type, op1, op2, op3
860 | ASM_SSE2_REG_REG_TXT_OP op, type, op1, op2, op3
1146 if (ctx->ir_base[insn->op1].op == IR_RLOAD) {
1155 if (insn->op1 != insn->op2) {
1211 if (IR_IS_CONST_REF(insn->op2) && insn->op1 != insn->op2) {
1220 if (IR_IS_CONST_REF(insn->op1)) {
1221 const ir_insn *val_insn = &ctx->ir_base[insn->op1];
1224 } else if (ir_rule(ctx, insn->op1) == IR_STATIC_ALLOCA) {
1227 } else if (ir_rule(ctx, insn->op1) & IR_FUSED) {
1231 if (insn->op1 != insn->op2) {
1247 if (IR_IS_CONST_REF(insn->op1)) {
1248 const ir_insn *val_insn = &ctx->ir_base[insn->op1];
1256 if (IR_IS_CONST_REF(insn->op1)) {
1263 if (!IR_IS_TYPE_INT(ctx->ir_base[insn->op1].type)) {
1441 if (IR_IS_CONST_REF(insn->op1)) {
1467 if (IR_IS_TYPE_INT(insn->type) && IR_IS_TYPE_INT(ctx->ir_base[insn->op1].type)) {
1479 if (IR_IS_CONST_REF(insn->op1)) {
1480 …constraints->tmp_regs[0] = IR_TMP_REG(1, ctx->ir_base[insn->op1].type, IR_LOAD_SUB_REF, IR_DEF_SUB…
1556 SWAP_REFS(insn->op1, insn->op2);
1564 if (insn->op1 == insn->op2) {
1569 } else if (ir_match_try_fuse_load(ctx, insn->op1, ref)) {
1618 if (insn->op1 == ref) {
1631 } else if (insn->op2 == ref && insn->op1 != insn->op2) {
1760 } else if (ir_match_try_fuse_load(ctx, insn->op1, root)) {
1769 && (IR_IS_CONST_REF(insn->op1) || ir_match_try_fuse_load(ctx, insn->op1, root))) {
1778 ir_match_fuse_load(ctx, insn->op1, root);
1780 && ir_match_try_fuse_load(ctx, insn->op1, root)) {
1792 ir_match_fuse_load(ctx, insn->op1, root);
1794 && ir_match_try_fuse_load(ctx, insn->op1, root)) {
1812 …else if ((IR_IS_CONST_REF(insn->op1) && !IR_IS_FP_ZERO(ctx->ir_base[insn->op1])) || ir_match_try_f…
1839 …else if ((IR_IS_CONST_REF(insn->op1) && !IR_IS_FP_ZERO(ctx->ir_base[insn->op1])) || ir_match_try_f…
1933 if (IR_IS_TYPE_INT(ctx->ir_base[insn->op1].type)) {
1937 && insn->op1 == ref - 1) { /* previous instruction */
1938 ir_insn *op1_insn = &ctx->ir_base[insn->op1];
1940 if (op1_insn->op == IR_AND && ctx->use_lists[insn->op1].count == 1) {
1943 ctx->rules[insn->op1] = IR_FUSED | IR_TEST_INT;
1953 ctx->rules[insn->op1] = IR_BINOP_INT | IR_MAY_SWAP;
1956 ctx->rules[insn->op1] = IR_BINOP_INT;
1973 if (IR_IS_CONST_REF(insn->op1)) {
1986 if (ctx->use_lists[insn->op1].count == 1 || ir_match_fuse_addr_all_useges(ctx, insn->op1)) {
1987 uint32_t rule = ctx->rules[insn->op1];
1990 ctx->rules[insn->op1] = rule = ir_match_insn(ctx, insn->op1);
1994 ctx->rules[insn->op1] = IR_FUSED | IR_SIMPLE | IR_LEA_SI;
1998 ctx->rules[insn->op1] = IR_FUSED | IR_SIMPLE | IR_LEA_SIB;
2002 ctx->rules[insn->op1] = IR_FUSED | IR_SIMPLE | IR_LEA_IB;
2005 ctx->rules[insn->op1] = IR_FUSED | IR_SIMPLE | IR_LEA_B_SI;
2008 ctx->rules[insn->op1] = IR_FUSED | IR_SIMPLE | IR_LEA_SI_B;
2034 if (insn->op1 != insn->op2) {
2035 if (ctx->use_lists[insn->op1].count == 1 || ir_match_fuse_addr_all_useges(ctx, insn->op1)) {
2036 uint32_t rule =ctx->rules[insn->op1];
2038 ctx->rules[insn->op1] = rule = ir_match_insn(ctx, insn->op1);
2041 ctx->rules[insn->op1] = IR_FUSED | IR_SIMPLE | IR_LEA_OB;
2056 ctx->rules[insn->op1] = IR_FUSED | IR_SIMPLE | IR_LEA_SI;
2124 } else if (IR_IS_CONST_REF(insn->op1)) {
2144 && !IR_IS_CONST_REF(insn->op1)) {
2146 ir_match_fuse_load(ctx, insn->op1, ref);
2172 && !IR_IS_CONST_REF(insn->op1)) {
2174 ir_match_fuse_load(ctx, insn->op1, ref);
2188 } else if (IR_IS_CONST_REF(insn->op1)) {
2212 } else if (IR_IS_CONST_REF(insn->op1)) {
2228 IR_ASSERT(IR_IS_TYPE_INT(ctx->ir_base[insn->op1].type)); // TODO: IR_BOOL_NOT_FP
2252 } else if (IR_IS_CONST_REF(insn->op1)) {
2266 } else if (IR_IS_CONST_REF(insn->op1)) {
2280 } else if (IR_IS_CONST_REF(insn->op1)) {
2291 } else if (IR_IS_CONST_REF(insn->op1)) {
2297 // lea [op1*2]
2299 // lea [op1*4]
2301 // lea [op1*8]
2317 } else if (IR_IS_CONST_REF(insn->op1)) {
2400 if (insn->op1 == op_insn->op1
2401 && ctx->ir_base[op_insn->op1].op == load_op
2402 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2403 && ctx->use_lists[op_insn->op1].count == 2) {
2406 ctx->rules[op_insn->op1] = IR_SKIPPED | load_op;
2413 && insn->op1 == op_insn->op2
2420 ctx->rules[op_insn->op1] = IR_SKIPPED | load_op;
2424 if (insn->op1 == op_insn->op1
2425 && ctx->ir_base[op_insn->op1].op == load_op
2426 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2427 && ctx->use_lists[op_insn->op1].count == 2) {
2430 ctx->rules[op_insn->op1] = IR_SKIPPED | load_op;
2434 if (insn->op1 == op_insn->op1
2435 && ctx->ir_base[op_insn->op1].op == load_op
2436 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2437 && ctx->use_lists[op_insn->op1].count == 2){
2440 ctx->rules[op_insn->op1] = IR_SKIPPED | load_op;
2444 if (insn->op1 == op_insn->op1
2445 && ctx->ir_base[op_insn->op1].op == load_op
2446 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2447 && ctx->use_lists[op_insn->op1].count == 2) {
2450 ctx->rules[op_insn->op1] = IR_SKIPPED | load_op;
2454 if (insn->op1 == op_insn->op1
2455 && ctx->ir_base[op_insn->op1].op == load_op
2456 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2457 && ctx->use_lists[op_insn->op1].count == 2) {
2460 ctx->rules[op_insn->op1] = IR_SKIPPED | load_op;
2464 if (insn->op1 == op_insn->op1
2465 && ctx->ir_base[op_insn->op1].op == load_op
2466 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2467 && ctx->use_lists[op_insn->op1].count == 2) {
2470 ctx->rules[op_insn->op1] = IR_SKIPPED | load_op;
2474 if (insn->op1 == op_insn->op1
2475 && ctx->ir_base[op_insn->op1].op == load_op
2476 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2477 && ctx->use_lists[op_insn->op1].count == 2) {
2480 ctx->rules[op_insn->op1] = IR_SKIPPED | load_op;
2484 if (insn->op1 == op_insn->op1
2485 && ctx->ir_base[op_insn->op1].op == load_op
2486 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2487 && ctx->use_lists[op_insn->op1].count == 2) {
2490 ctx->rules[op_insn->op1] = IR_SKIPPED | load_op;
2494 if (insn->op1 == op_insn->op1
2495 && ctx->ir_base[op_insn->op1].op == load_op
2496 && ctx->ir_base[op_insn->op1].op2 == insn->op2
2497 && ctx->use_lists[op_insn->op1].count == 2) {
2500 ctx->rules[op_insn->op1] = IR_SKIPPED | load_op;
2551 if (insn->op1 == op_insn->op1
2552 && ctx->ir_base[op_insn->op1].op == IR_RLOAD
2553 && ctx->ir_base[op_insn->op1].op2 == insn->op3
2554 && ctx->use_lists[op_insn->op1].count == 2) {
2557 ctx->rules[op_insn->op1] = IR_SKIPPED | IR_RLOAD;
2560 && insn->op1 == op_insn->op2
2567 ctx->rules[op_insn->op1] = IR_SKIPPED | IR_RLOAD;
2597 if (IR_IS_TYPE_INT(ctx->ir_base[op2_insn->op1].type)) {
2601 && op2_insn->op1 == insn->op2 - 1) { /* previous instruction */
2602 ir_insn *op1_insn = &ctx->ir_base[op2_insn->op1];
2604 if (op1_insn->op == IR_AND && ctx->use_lists[op2_insn->op1].count == 1) {
2607 ctx->rules[op2_insn->op1] = IR_FUSED | IR_TEST_INT;
2619 ctx->rules[op2_insn->op1] = IR_BINOP_INT | IR_MAY_SWAP;
2622 ctx->rules[op2_insn->op1] = IR_BINOP_INT;
2670 && insn->op1 == ref - 1 /* previous instruction */
2674 ir_insn *store_insn = &ctx->ir_base[insn->op1];
2685 if (ctx->ir_base[op_insn->op1].op == IR_LOAD
2686 && ctx->ir_base[op_insn->op1].op2 == store_insn->op2) {
2687 if (ir_in_same_block(ctx, op_insn->op1)
2688 && ctx->use_lists[op_insn->op1].count == 2
2689 && store_insn->op1 == op_insn->op1) {
2692 ctx->rules[op_insn->op1] = IR_SKIPPED | IR_LOAD;
2694 ctx->rules[insn->op1] = IR_MEM_BINOP_INT;
2702 && store_insn->op1 == op_insn->op2) {
2706 ctx->rules[op_insn->op1] = IR_SKIPPED | IR_LOAD;
2708 ctx->rules[insn->op1] = IR_MEM_BINOP_INT;
2722 if (!IR_IS_CONST_REF(insn->op1) && ctx->use_lists[insn->op1].count == 1) {
2723 ir_insn *op1_insn = &ctx->ir_base[insn->op1];
2726 if (IR_IS_TYPE_INT(ctx->ir_base[op1_insn->op1].type)) {
2728 ctx->rules[insn->op1] = IR_FUSED | IR_CMP_INT;
2732 ctx->rules[insn->op1] = IR_FUSED | IR_CMP_FP;
2747 if (IR_IS_TYPE_INT(ctx->ir_base[op2_insn->op1].type)) {
2751 if (op2_insn->op1 == insn->op2 - 1) { /* previous instruction */
2752 ir_insn *op1_insn = &ctx->ir_base[op2_insn->op1];
2761 ctx->rules[op2_insn->op1] = IR_BINOP_INT | IR_MAY_SWAP;
2764 ctx->rules[op2_insn->op1] = IR_BINOP_INT;
2771 && op2_insn->op1 == insn->op2 - 2 /* before previous instruction */
2772 && ir_in_same_block(ctx, op2_insn->op1)
2773 && ctx->use_lists[op2_insn->op1].count == 2) {
2776 if (store_insn->op == IR_STORE && store_insn->op3 == op2_insn->op1) {
2777 ir_insn *op_insn = &ctx->ir_base[op2_insn->op1];
2784 if (ctx->ir_base[op_insn->op1].op == IR_LOAD
2785 && ctx->ir_base[op_insn->op1].op2 == store_insn->op2) {
2786 if (ir_in_same_block(ctx, op_insn->op1)
2787 && ctx->use_lists[op_insn->op1].count == 2
2788 && store_insn->op1 == op_insn->op1) {
2790 ctx->rules[op2_insn->op1] = IR_FUSED | IR_BINOP_INT;
2791 ctx->rules[op_insn->op1] = IR_SKIPPED | IR_LOAD;
2802 && store_insn->op1 == op_insn->op2) {
2805 ctx->rules[op2_insn->op1] = IR_FUSED | IR_BINOP_INT;
2806 ctx->rules[op_insn->op1] = IR_SKIPPED | IR_LOAD;
2841 …if (ir_type_size[ctx->ir_base[insn->op1].type] > (IR_IS_TYPE_SIGNED(ctx->ir_base[insn->op1].type) …
2842 ir_match_fuse_load(ctx, insn->op1, ref);
2849 ir_match_fuse_load(ctx, insn->op1, ref);
2853 ir_match_fuse_load(ctx, insn->op1, ref);
2856 ir_match_fuse_load(ctx, insn->op1, ref);
2857 if (IR_IS_TYPE_INT(insn->type) && IR_IS_TYPE_INT(ctx->ir_base[insn->op1].type)) {
2864 ir_match_fuse_load(ctx, insn->op1, ref);
2867 ir_match_fuse_load(ctx, insn->op1, ref);
3099 var_insn = &ctx->ir_base[var_insn->op1];
3315 if (ir_rule(ctx, insn->op1) == IR_STATIC_ALLOCA) {
3316 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op1].op3);
3337 if (ir_rule(ctx, insn->op1) == IR_STATIC_ALLOCA) {
3338 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op1].op3);
3355 op1_insn = &ctx->ir_base[insn->op1];
3362 index_reg_ref = insn->op1 * sizeof(ir_ref) + 1;
3363 } else if (ir_rule(ctx, op1_insn->op1) == IR_STATIC_ALLOCA) {
3364 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[op1_insn->op1].op3);
3369 base_reg_ref = insn->op1 * sizeof(ir_ref) + 1;
3377 if (ir_rule(ctx, insn->op1) == IR_STATIC_ALLOCA) {
3378 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op1].op3);
3382 } else if (ir_rule(ctx, op2_insn->op1) == IR_STATIC_ALLOCA) {
3383 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[op2_insn->op1].op3);
3393 index_reg_ref = insn->op1 * sizeof(ir_ref) + 1;
3394 op1_insn = &ctx->ir_base[insn->op1];
3400 base_reg_ref = index_reg_ref = insn->op1 * sizeof(ir_ref) + 1;
3401 op1_insn = &ctx->ir_base[insn->op1];
3406 op1_insn = &ctx->ir_base[insn->op1];
3413 index_reg_ref = insn->op1 * sizeof(ir_ref) + 1;
3414 } else if (ir_rule(ctx, op1_insn->op1) == IR_STATIC_ALLOCA) {
3415 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[op1_insn->op1].op3);
3418 index_reg_ref = insn->op1 * sizeof(ir_ref) + 2;
3420 base_reg_ref = insn->op1 * sizeof(ir_ref) + 1;
3421 index_reg_ref = insn->op1 * sizeof(ir_ref) + 2;
3426 op1_insn = &ctx->ir_base[insn->op1];
3430 if (ir_rule(ctx, op1_insn->op1) == IR_STATIC_ALLOCA) {
3431 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[op1_insn->op1].op3);
3435 base_reg_ref = insn->op1 * sizeof(ir_ref) + 1;
3439 index_reg_ref = insn->op1 * sizeof(ir_ref) + 1;
3440 op1_insn = &ctx->ir_base[insn->op1];
3444 if (ir_rule(ctx, op2_insn->op1) == IR_STATIC_ALLOCA) {
3445 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[op2_insn->op1].op3);
3453 if (ir_rule(ctx, insn->op1) == IR_STATIC_ALLOCA) {
3454 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op1].op3);
3466 index_reg_ref = insn->op1 * sizeof(ir_ref) + 1;
3474 op1_insn = &ctx->ir_base[insn->op1];
3480 op1_insn = &ctx->ir_base[insn->op1];
3481 base_reg_ref = insn->op1 * sizeof(ir_ref) + 1;
3488 op1_insn = &ctx->ir_base[insn->op1];
3489 index_reg_ref = op1_insn->op1 * sizeof(ir_ref) + 1;
3490 base_reg_ref = insn->op1 * sizeof(ir_ref) + 2;
3491 op1_insn = &ctx->ir_base[op1_insn->op1];
3825 ir_ref op1 = insn->op1;
3835 ir_emit_load(ctx, type, op1_reg, op1);
3841 ir_emit_load(ctx, type, def_reg, op1);
3843 if (op1 == op2) {
3851 if (op1 != op2) {
3952 ir_ref op1 = insn->op1;
3959 IR_ASSERT(!IR_IS_CONST_REF(op1));
3964 ir_emit_load(ctx, type, op1_reg, op1);
3984 if (ir_rule(ctx, op1) & IR_FUSED) {
3985 mem = ir_fuse_load(ctx, def, op1);
3987 mem = ir_ref_spill_slot(ctx, op1);
4001 ir_ref op1 = insn->op1;
4011 ir_emit_load(ctx, type, op1_reg, op1);
4017 ir_emit_load(ctx, type, def_reg, op1);
4023 if (op1 != op2) {
4028 if (op1 == op2) {
4058 ir_type type = ctx->ir_base[insn->op1].type;
4077 ir_type type = ctx->ir_base[overflow_insn->op1].type;
4245 ir_ref op1 = insn->op1;
4255 ir_emit_load(ctx, type, op1_reg, op1);
4261 ir_emit_load(ctx, type, def_reg, op1);
4304 ir_ref op1 = insn->op1;
4317 ir_emit_load(ctx, type, op1_reg, op1);
4367 ir_ref op1 = insn->op1;
4381 ir_emit_load(ctx, type, op1_reg, op1);
4387 ir_emit_load(ctx, type, def_reg, op1);
4468 ir_emit_load(ctx, type, op1_reg, insn->op1);
4489 ir_emit_load(ctx, type, def_reg, insn->op1);
4571 ir_ref op1 = insn->op1;
4582 ir_emit_load(ctx, type, op1_reg, op1);
4588 ir_emit_load(ctx, type, def_reg, op1);
4661 ir_ref op1 = insn->op1;
4669 ir_emit_load(ctx, type, op1_reg, op1);
4675 ir_emit_load(ctx, type, def_reg, op1);
4712 ir_ref op1 = insn->op1;
4721 ir_emit_load(ctx, type, op1_reg, op1);
4802 if (ir_rule(ctx, op1) & IR_FUSED) {
4803 mem = ir_fuse_load(ctx, def, op1);
4805 mem = ir_ref_spill_slot(ctx, op1);
4879 ir_ref op1 = insn->op1;
4889 ir_emit_load(ctx, type, def_reg, op1);
4898 ir_emit_load(ctx, type, op1_reg, op1);
5036 ir_ref op1 = insn->op1;
5044 ir_emit_load(ctx, type, op1_reg, op1);
5061 ir_type type = ctx->ir_base[insn->op1].type;
5062 ir_ref op1 = insn->op1;
5070 ir_emit_load(ctx, type, op1_reg, op1);
5076 ir_mem mem = ir_ref_spill_slot(ctx, op1);
5092 ir_ref op1 = insn->op1;
5101 ir_emit_load(ctx, type, op1_reg, op1);
5107 ir_emit_load(ctx, type, IR_REG_RAX, op1);
5110 if (op2_reg == IR_REG_NONE && op1 == op2) {
5247 ir_ref op1 = insn->op1;
5255 ir_emit_load(ctx, type, op1_reg, op1);
5261 ir_emit_load(ctx, type, def_reg, op1);
5338 ir_ref op1 = insn->op1;
5348 ir_emit_load(ctx, type, op1_reg, op1);
5354 ir_emit_load(ctx, type, def_reg, op1);
5356 if (op1 == op2) {
5363 if (op1 != op2) {
5455 ir_ref op1 = insn->op1;
5465 ir_emit_load(ctx, type, op1_reg, op1);
5470 if (op1 != op2) {
5557 …ctx *ctx, ir_type type, ir_ref root, ir_insn *insn, ir_reg op1_reg, ir_ref op1, ir_reg op2_reg, ir…
5580 } else if (IR_IS_CONST_REF(op1)) {
5585 if (ir_rule(ctx, op1) & IR_FUSED) {
5586 mem = ir_fuse_load(ctx, root, op1);
5588 mem = ir_ref_spill_slot(ctx, op1);
5601 ir_type type = ctx->ir_base[cmp_insn->op1].type;
5602 ir_ref op1 = cmp_insn->op1;
5609 ir_emit_load(ctx, type, op1_reg, op1);
5613 if (op1 != op2) {
5618 ir_emit_cmp_int_common(ctx, type, root, cmp_insn, op1_reg, op1, op2_reg, op2);
5716 ir_type type = ctx->ir_base[insn->op1].type;
5718 ir_ref op1 = insn->op1;
5727 ir_emit_load(ctx, type, op1_reg, op1);
5731 if (op1 != op2) {
5756 ir_emit_cmp_int_common(ctx, type, def, insn, op1_reg, op1, op2_reg, op2);
5769 ir_ref op1 = binop_insn->op1;
5778 ir_emit_load(ctx, type, op1_reg, op1);
5783 if (op1 != op2) {
5822 } else if (IR_IS_CONST_REF(op1)) {
5827 if (ir_rule(ctx, op1) & IR_FUSED) {
5828 mem = ir_fuse_load(ctx, root, op1);
5830 mem = ir_ref_spill_slot(ctx, op1);
5835 if (op1 != op2) {
5841 IR_ASSERT(!IR_IS_CONST_REF(op1));
5853 ir_emit_test_int_common(ctx, def, insn->op1, insn->op);
5875 ir_type type = ctx->ir_base[cmp_insn->op1].type;
5877 ir_ref op1, op2;
5880 op1 = cmp_insn->op1;
5888 SWAP_REFS(op1, op2);
5898 ir_emit_load(ctx, type, op1_reg, op1);
5903 if (op1 != op2) {
6141 ir_type type = ctx->ir_base[cmp_insn->op1].type;
6142 ir_ref op1 = cmp_insn->op1;
6149 ir_emit_load(ctx, type, op1_reg, op1);
6153 if (op1 != op2) {
6174 ir_insn *prev_insn = &ctx->ir_base[insn->op1];
6176 if (ir_rule(ctx, prev_insn->op1) == IR_CMP_AND_BRANCH_INT) {
6177 prev_insn = &ctx->ir_base[prev_insn->op1];
6179 if (prev_insn->op1 == cmp_insn->op1 && prev_insn->op2 == cmp_insn->op2) {
6185 ir_emit_cmp_int_common(ctx, type, def, cmp_insn, op1_reg, op1, op2_reg, op2);
6196 op2 = ctx->ir_base[op2].op1;
6265 ir_ref op1 = insn->op1;
6268 ir_type op1_type = ctx->ir_base[op1].type;
6280 if (op1 == op2) {
6287 if (op1 == op2) {
6295 if (op1 == op2) {
6302 if (op1 == op3) {
6306 if (op1_reg != IR_REG_NONE && op1 != op2 && op1 != op3 && IR_REG_SPILLED(op1_reg)) {
6308 ir_emit_load(ctx, op1_type, op1_reg, op1);
6315 ir_mem mem = ir_ref_spill_slot(ctx, op1);
6429 ir_emit_cmp_int_common2(ctx, def, insn->op1, &ctx->ir_base[insn->op1]);
6430 op = ctx->ir_base[insn->op1].op;
6593 op = ir_emit_cmp_fp_common(ctx, def, insn->op1, &ctx->ir_base[insn->op1]);
6750 ir_type src_type = ctx->ir_base[insn->op1].type;
6764 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
6796 } else if (IR_IS_CONST_REF(insn->op1)) {
6800 val = ctx->ir_base[insn->op1].val.i8;
6802 val = ctx->ir_base[insn->op1].val.i16;
6804 val = ctx->ir_base[insn->op1].val.i32;
6807 val = ctx->ir_base[insn->op1].val.i64;
6813 if (ir_rule(ctx, insn->op1) & IR_FUSED) {
6814 mem = ir_fuse_load(ctx, def, insn->op1);
6816 mem = ir_ref_spill_slot(ctx, insn->op1);
6858 ir_type src_type = ctx->ir_base[insn->op1].type;
6872 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
6907 } else if (IR_IS_CONST_REF(insn->op1)) {
6911 val = ctx->ir_base[insn->op1].val.u8;
6913 val = ctx->ir_base[insn->op1].val.u16;
6915 val = ctx->ir_base[insn->op1].val.u32;
6918 val = ctx->ir_base[insn->op1].val.u64;
6924 if (ir_rule(ctx, insn->op1) & IR_FUSED) {
6925 mem = ir_fuse_load(ctx, def, insn->op1);
6927 mem = ir_ref_spill_slot(ctx, insn->op1);
6968 ir_type src_type = ctx->ir_base[insn->op1].type;
6979 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
6985 ir_emit_load_ex(ctx, dst_type, def_reg, insn->op1, def);
6995 ir_type src_type = ctx->ir_base[insn->op1].type;
7007 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
7013 ir_emit_load_ex(ctx, dst_type, def_reg, insn->op1, def);
7019 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
7025 ir_emit_load_ex(ctx, dst_type, def_reg, insn->op1, def);
7032 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
7051 } else if (IR_IS_CONST_REF(insn->op1)) {
7052 ir_insn *_insn = &ctx->ir_base[insn->op1];
7066 if (ir_rule(ctx, insn->op1) & IR_FUSED) {
7067 mem = ir_fuse_load(ctx, def, insn->op1);
7069 mem = ir_ref_spill_slot(ctx, insn->op1);
7087 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
7106 } else if (IR_IS_CONST_REF(insn->op1)) {
7107 int label = ir_const_label(ctx, insn->op1);
7113 if (ir_rule(ctx, insn->op1) & IR_FUSED) {
7114 mem = ir_fuse_load(ctx, def, insn->op1);
7116 mem = ir_ref_spill_slot(ctx, insn->op1);
7130 ir_type src_type = ctx->ir_base[insn->op1].type;
7144 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
7228 } else if (IR_IS_CONST_REF(insn->op1)) {
7234 if (ir_rule(ctx, insn->op1) & IR_FUSED) {
7235 mem = ir_fuse_load(ctx, def, insn->op1);
7237 mem = ir_ref_spill_slot(ctx, insn->op1);
7291 ir_type src_type = ctx->ir_base[insn->op1].type;
7308 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
7344 } else if (IR_IS_CONST_REF(insn->op1)) {
7345 int label = ir_const_label(ctx, insn->op1);
7384 if (ir_rule(ctx, insn->op1) & IR_FUSED) {
7385 mem = ir_fuse_load(ctx, def, insn->op1);
7387 mem = ir_ref_spill_slot(ctx, insn->op1);
7433 ir_type src_type = ctx->ir_base[insn->op1].type;
7445 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
7465 } else if (IR_IS_CONST_REF(insn->op1)) {
7466 int label = ir_const_label(ctx, insn->op1);
7485 if (ir_rule(ctx, insn->op1) & IR_FUSED) {
7486 mem = ir_fuse_load(ctx, def, insn->op1);
7488 mem = ir_ref_spill_slot(ctx, insn->op1);
7520 ir_emit_load(ctx, type, op1_reg, insn->op1);
7527 ir_emit_load(ctx, type, def_reg, insn->op1);
7547 ir_emit_load(ctx, type, op1_reg, insn->op1);
7554 ir_emit_load(ctx, type, def_reg, insn->op1);
7576 mem = ir_var_spill_slot(ctx, insn->op1);
7803 ir_type type = ctx->ir_base[cmp_insn->op1].type;
7804 ir_ref op1 = cmp_insn->op1;
7825 ir_emit_load(ctx, type, op1_reg, op1);
7829 if (op1 != op2) {
7834 ir_emit_cmp_int_common(ctx, type, ref, cmp_insn, op1_reg, op1, op2_reg, op2);
9479 ir_type type = ctx->ir_base[cmp_insn->op1].type;
9480 ir_ref op1 = cmp_insn->op1;
9488 ir_emit_load(ctx, type, op1_reg, op1);
9492 if (op1 != op2) {
9523 ir_emit_cmp_int_common(ctx, type, def, cmp_insn, op1_reg, op1, op2_reg, op2);
9570 type = ctx->ir_base[ctx->ir_base[insn->op2].op1].type;
10283 …} else if (IR_IS_FOLDABLE_OP(insn->op) && j > 1 && input == insn->op1 && ctx->regs[i][1] != IR_REG…
