Lines Matching refs:op
72 |.macro ASM_EXPAND_OP_MEM, MACRO, op, type, op1
80 | MACRO op, type, [offset]
82 | MACRO op, type, [Ra(base)+offset]
86 | MACRO op, type, [Ra(index)*8+offset]
88 | MACRO op, type, [Ra(base)+Ra(index)*8+offset]
92 | MACRO op, type, [Ra(index)*4+offset]
94 | MACRO op, type, [Ra(base)+Ra(index)*4+offset]
98 | MACRO op, type, [Ra(index)*2+offset]
100 | MACRO op, type, [Ra(base)+Ra(index)*2+offset]
105 | MACRO op, type, [Ra(index)+offset]
107 | MACRO op, type, [Ra(base)+Ra(index)+offset]
113 |.macro ASM_EXPAND_OP1_MEM, MACRO, op, type, op1, op2
121 | MACRO op, type, [offset], op2
123 | MACRO op, type, [Ra(base)+offset], op2
127 | MACRO op, type, [Ra(index)*8+offset], op2
129 | MACRO op, type, [Ra(base)+Ra(index)*8+offset], op2
133 | MACRO op, type, [Ra(index)*4+offset], op2
135 | MACRO op, type, [Ra(base)+Ra(index)*4+offset], op2
139 | MACRO op, type, [Ra(index)*2+offset], op2
141 | MACRO op, type, [Ra(base)+Ra(index)*2+offset], op2
146 | MACRO op, type, [Ra(index)+offset], op2
148 | MACRO op, type, [Ra(base)+Ra(index)+offset], op2
154 |.macro ASM_EXPAND_OP2_MEM, MACRO, op, type, op1, op2
162 | MACRO op, type, op1, [offset]
164 | MACRO op, type, op1, [Ra(base)+offset]
168 | MACRO op, type, op1, [Ra(index)*8+offset]
170 | MACRO op, type, op1, [Ra(base)+Ra(index)*8+offset]
174 | MACRO op, type, op1, [Ra(index)*4+offset]
176 | MACRO op, type, op1, [Ra(base)+Ra(index)*4+offset]
180 | MACRO op, type, op1, [Ra(index)*2+offset]
182 | MACRO op, type, op1, [Ra(base)+Ra(index)*2+offset]
187 | MACRO op, type, op1, [Ra(index)+offset]
189 | MACRO op, type, op1, [Ra(base)+Ra(index)+offset]
195 |.macro ASM_EXPAND_OP2_MEM_3, MACRO, op, type, op1, op2, op3
203 | MACRO op, type, op1, [offset], op3
205 | MACRO op, type, op1, [Ra(base)+offset], op3
209 | MACRO op, type, op1, [Ra(index)*8+offset], op3
211 | MACRO op, type, op1, [Ra(base)+Ra(index)*8+offset], op3
215 | MACRO op, type, op1, [Ra(index)*4+offset], op3
217 | MACRO op, type, op1, [Ra(base)+Ra(index)*4+offset], op3
221 | MACRO op, type, op1, [Ra(index)*2+offset], op3
223 | MACRO op, type, op1, [Ra(base)+Ra(index)*2+offset], op3
228 | MACRO op, type, op1, [Ra(index)+offset], op3
230 | MACRO op, type, op1, [Ra(base)+Ra(index)+offset], op3
236 |.macro ASM_EXPAND_OP3_MEM, MACRO, op, type, op1, op2, op3
244 | MACRO op, type, op1, op2, [offset]
246 | MACRO op, type, op1, op2, [Ra(base)+offset]
250 | MACRO op, type, op1, op2, [Ra(index)*8+offset]
252 | MACRO op, type, op1, op2, [Ra(base)+Ra(index)*8+offset]
256 | MACRO op, type, op1, op2, [Ra(index)*4+offset]
258 | MACRO op, type, op1, op2, [Ra(base)+Ra(index)*4+offset]
262 | MACRO op, type, op1, op2, [Ra(index)*2+offset]
264 | MACRO op, type, op1, op2, [Ra(base)+Ra(index)*2+offset]
269 | MACRO op, type, op1, op2, [Ra(index)+offset]
271 | MACRO op, type, op1, op2, [Ra(base)+Ra(index)+offset]
277 |.macro ASM_EXPAND_TYPE_MEM, op, type, op1
282 | op byte op1
285 | op word op1
288 | op dword op1
292 | op qword op1
298 |.macro ASM_EXPAND_TYPE_MEM_REG, op, type, op1, op2
303 | op byte op1, Rb(op2)
306 | op word op1, Rw(op2)
309 | op dword op1, Rd(op2)
313 | op qword op1, Rq(op2)
319 |.macro ASM_EXPAND_TYPE_MEM_TXT, op, type, op1, op2
324 | op byte op1, op2
327 | op word op1, op2
330 | op dword op1, op2
334 | op qword op1, op2
340 |.macro ASM_EXPAND_TYPE_MEM_IMM, op, type, op1, op2
345 | op byte op1, (op2 & 0xff)
348 | op word op1, (op2 & 0xffff)
351 | op dword op1, op2
355 | op qword op1, op2
361 |.macro ASM_EXPAND_TYPE_REG_MEM, op, type, op1, op2
366 | op Rb(op1), byte op2
369 | op Rw(op1), word op2
372 | op Rd(op1), dword op2
376 | op Rq(op1), qword op2
382 |.macro ASM_TMEM_OP, op, type, op1
390 | op type [offset]
392 | op type [Ra(base)+offset]
396 | op type [Ra(index)*8+offset]
398 | op type [Ra(base)+Ra(index)*8+offset]
402 | op type [Ra(index)*4+offset]
404 | op type [Ra(base)+Ra(index)*4+offset]
408 | op type [Ra(index)*2+offset]
410 | op type [Ra(base)+Ra(index)*2+offset]
415 | op type [Ra(index)+offset]
417 | op type [Ra(base)+Ra(index)+offset]
423 |.macro ASM_TXT_TMEM_OP, op, op1, type, op2
431 | op op1, type [offset]
433 | op op1, type [Ra(base)+offset]
437 | op op1, type [Ra(index)*8+offset]
439 | op op1, type [Ra(base)+Ra(index)*8+offset]
443 | op op1, type [Ra(index)*4+offset]
445 | op op1, type [Ra(base)+Ra(index)*4+offset]
449 | op op1, type [Ra(index)*2+offset]
451 | op op1, type [Ra(base)+Ra(index)*2+offset]
456 | op op1, type [Ra(index)+offset]
458 | op op1, type [Ra(base)+Ra(index)+offset]
464 |.macro ASM_TMEM_TXT_OP, op, type, op1, op2
472 | op type [offset], op2
474 | op type [Ra(base)+offset], op2
478 | op type [Ra(index)*8+offset], op2
480 | op type [Ra(base)+Ra(index)*8+offset], op2
484 | op type [Ra(index)*4+offset], op2
486 | op type [Ra(base)+Ra(index)*4+offset], op2
490 | op type [Ra(index)*2+offset], op2
492 | op type [Ra(base)+Ra(index)*2+offset], op2
497 | op type [Ra(index)+offset], op2
499 | op type [Ra(base)+Ra(index)+offset], op2
505 |.macro ASM_TXT_TXT_TMEM_OP, op, op1, op2, type, op3
513 | op op1, op2, type [offset]
515 | op op1, op2, type [Ra(base)+offset]
519 | op op1, op2, type [Ra(index)*8+offset]
521 | op op1, op2, type [Ra(base)+Ra(index)*8+offset]
525 | op op1, op2, type [Ra(index)*4+offset]
527 | op op1, op2, type [Ra(base)+Ra(index)*4+offset]
531 | op op1, op2, type [Ra(index)*2+offset]
533 | op op1, op2, type [Ra(base)+Ra(index)*2+offset]
538 | op op1, op2, type [Ra(index)+offset]
540 | op op1, op2, type [Ra(base)+Ra(index)+offset]
546 |.macro ASM_REG_OP, op, type, op1
551 | op Rb(op1)
554 | op Rw(op1)
557 | op Rd(op1)
561 | op Rq(op1)
567 |.macro ASM_MEM_OP, op, type, op1
568 | ASM_EXPAND_OP_MEM ASM_EXPAND_TYPE_MEM, op, type, op1
571 |.macro ASM_REG_REG_OP, op, type, op1, op2
576 | op Rb(op1), Rb(op2)
579 | op Rw(op1), Rw(op2)
582 | op Rd(op1), Rd(op2)
586 | op Rq(op1), Rq(op2)
592 |.macro ASM_REG_REG_OP2, op, type, op1, op2
598 | op Rw(op1), Rw(op2)
601 | op Rd(op1), Rd(op2)
605 | op Rq(op1), Rq(op2)
611 |.macro ASM_REG_TXT_OP, op, type, op1, op2
616 | op Rb(op1), op2
619 | op Rw(op1), op2
622 | op Rd(op1), op2
626 | op Rq(op1), op2
632 |.macro ASM_REG_IMM_OP, op, type, op1, op2
637 | op Rb(op1), (op2 & 0xff)
640 | op Rw(op1), (op2 & 0xffff)
643 | op Rd(op1), op2
647 | op Rq(op1), op2
653 |.macro ASM_MEM_REG_OP, op, type, op1, op2
654 | ASM_EXPAND_OP1_MEM ASM_EXPAND_TYPE_MEM_REG, op, type, op1, op2
657 |.macro ASM_MEM_TXT_OP, op, type, op1, op2
658 | ASM_EXPAND_OP1_MEM ASM_EXPAND_TYPE_MEM_TXT, op, type, op1, op2
661 |.macro ASM_MEM_IMM_OP, op, type, op1, op2
662 | ASM_EXPAND_OP1_MEM ASM_EXPAND_TYPE_MEM_IMM, op, type, op1, op2
665 |.macro ASM_REG_MEM_OP, op, type, op1, op2
666 | ASM_EXPAND_OP2_MEM ASM_REG_TXT_OP, op, type, op1, op2
669 |.macro ASM_REG_REG_MUL, op, type, op1, op2
674 | op Rw(op1), Rw(op2)
677 | op Rd(op1), Rd(op2)
681 | op Rq(op1), Rq(op2)
687 |.macro ASM_REG_IMM_MUL, op, type, op1, op2
692 | op Rw(op1), op2
695 | op Rd(op1), op2
699 | op Rq(op1), op2
705 |.macro ASM_REG_TXT_MUL, op, type, op1, op2
710 | op Rw(op1), op2
713 | op Rd(op1), op2
717 | op Rq(op1), op2
723 |.macro ASM_REG_MEM_MUL, op, type, op1, op2
724 | ASM_EXPAND_OP2_MEM ASM_REG_TXT_MUL, op, type, op1, op2
727 |.macro ASM_REG_TXT_TXT_MUL, op, type, op1, op2, op3
732 | op Rw(op1), op2, op3
735 | op Rd(op1), op2, op3
739 | op Rq(op1), op2, op3
745 |.macro ASM_REG_MEM_TXT_MUL, op, type, op1, op2, op3
749 |.macro ASM_SSE2_REG_REG_OP, op, type, op1, op2
751 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST)
754 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST)
758 |.macro ASM_SSE2_REG_TXT_OP, op, type, op1, op2
760 | op..d xmm(op1-IR_REG_FP_FIRST), qword op2
763 | op..s xmm(op1-IR_REG_FP_FIRST), dword op2
767 |.macro ASM_SSE2_REG_MEM_OP, op, type, op1, op2
768 | ASM_EXPAND_OP2_MEM ASM_SSE2_REG_TXT_OP, op, type, op1, op2
771 |.macro ASM_AVX_REG_REG_REG_OP, op, type, op1, op2, op3
773 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), xmm(op3-IR_REG_FP_FIRST)
776 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), xmm(op3-IR_REG_FP_FIRST)
780 |.macro ASM_AVX_REG_REG_TXT_OP, op, type, op1, op2, op3
782 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), qword op3
785 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), dword op3
789 |.macro ASM_AVX_REG_REG_MEM_OP, op, type, op1, op2, op3
790 | ASM_EXPAND_OP3_MEM ASM_AVX_REG_REG_TXT_OP, op, type, op1, op2, op3
793 |.macro ASM_FP_REG_REG_OP, op, type, op1, op2
795 | ASM_SSE2_REG_REG_OP v..op, type, op1, op2
797 | ASM_SSE2_REG_REG_OP op, type, op1, op2
801 |.macro ASM_FP_TXT_REG_OP, op, type, dst, src
804 | v..op..d qword dst, xmm(src-IR_REG_FP_FIRST)
806 | op..d qword dst, xmm(src-IR_REG_FP_FIRST)
811 | v..op..s dword dst, xmm(src-IR_REG_FP_FIRST)
813 | op..s dword dst, xmm(src-IR_REG_FP_FIRST)
818 |.macro ASM_FP_MEM_REG_OP, op, type, op1, op2
819 | ASM_EXPAND_OP1_MEM ASM_FP_TXT_REG_OP, op, type, op1, op2
822 |.macro ASM_FP_REG_TXT_OP, op, type, op1, op2
824 | ASM_SSE2_REG_TXT_OP v..op, type, op1, op2
826 | ASM_SSE2_REG_TXT_OP op, type, op1, op2
830 |.macro ASM_FP_REG_MEM_OP, op, type, op1, op2
832 | ASM_SSE2_REG_MEM_OP v..op, type, op1, op2
834 | ASM_SSE2_REG_MEM_OP op, type, op1, op2
838 |.macro ASM_SSE2_REG_REG_TXT_OP, op, type, op1, op2, op3
840 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), op3
843 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), op3
847 |.macro ASM_SSE2_REG_REG_REG_TXT_OP, op, type, op1, op2, op3, op4
849 | op..d xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), xmm(op3-IR_REG_FP_FIRST), op4
852 | op..s xmm(op1-IR_REG_FP_FIRST), xmm(op2-IR_REG_FP_FIRST), xmm(op3-IR_REG_FP_FIRST), op4
856 |.macro ASM_FP_REG_REG_TXT_OP, op, type, op1, op2, op3
858 | ASM_SSE2_REG_REG_REG_TXT_OP v..op, type, op1, op2, op3
860 | ASM_SSE2_REG_REG_TXT_OP op, type, op1, op2, op3
1086 } else if (IR_IS_SYM_CONST(addr_insn->op)) {
1103 } else if (IR_IS_SYM_CONST(val_insn->op)) {
1144 if (ctx->ir_base[insn->op1].op == IR_RLOAD) {
1578 if (insn->op != IR_LOAD && (insn->op != IR_STORE || insn->op3 == addr_ref)) {
1593 if (insn->op == IR_ADD) {
1597 if (IR_IS_SYM_CONST(op2_insn->op)) {
1626 if (insn->op == IR_MUL
1629 if (!IR_IS_SYM_CONST(insn->op)
1661 if (insn->op == IR_STORE) {
1664 } else if (insn->op == IR_CALL) {
1676 && ctx->ir_base[ref].op == IR_LOAD) {
1701 && insn->op == IR_LOAD) {
1718 } else if (insn->op == IR_PARAM) {
1723 } else if (ctx->ir_base[ref].op == IR_VLOAD) {
1758 if (insn->op != IR_EQ && insn->op != IR_NE) {
1759 insn->op ^= 3;
1777 if (insn->op != IR_EQ && insn->op != IR_NE) {
1778 if (insn->op == IR_LT || insn->op == IR_LE) {
1781 insn->op ^= 3;
1790 if (insn->op != IR_EQ && insn->op != IR_NE) {
1791 insn->op ^= 3;
1799 if (insn->op == IR_LT || insn->op == IR_LE) {
1802 insn->op ^= 3;
1805 if (insn->op == IR_GT || insn->op == IR_GE) {
1808 insn->op ^= 3;
1817 if (insn->op != IR_EQ && insn->op != IR_NE) {
1818 insn->op ^= 3;
1898 switch (insn->op) {
1911 && !IR_IS_SYM_CONST(ctx->ir_base[insn->op2].op)
1916 if (op1_insn->op == IR_AND && ctx->use_lists[insn->op1].count == 1) {
1921 } else if ((op1_insn->op == IR_OR || op1_insn->op == IR_AND || op1_insn->op == IR_XOR) ||
1923 ((op1_insn->op == IR_ADD || op1_insn->op == IR_SUB) &&
1924 (insn->op == IR_EQ || insn->op == IR_NE))) {
1926 if (ir_op_flags[op1_insn->op] & IR_OP_FLAG_COMMUTATIVE) {
1951 } else if (IR_IS_SYM_CONST(op2_insn->op)) {
1952 if (insn->op == IR_ADD && ir_may_fuse_addr(ctx, op2_insn)) {
1958 …} else if ((ir_type_size[insn->type] >= 4 && insn->op == IR_ADD && IR_IS_SIGNED_32BIT(op2_insn->va…
1959 …(ir_type_size[insn->type] >= 4 && insn->op == IR_SUB && IR_IS_SIGNED_NEG_32BIT(op2_insn->val.i64))…
1984 if (insn->op == IR_ADD) {
2002 … } else if ((ctx->flags & IR_OPT_CODEGEN) && insn->op == IR_ADD && ir_type_size[insn->type] >= 4) {
2061 if (ir_op_flags[insn->op] & IR_OP_FLAG_COMMUTATIVE) {
2070 if (ir_op_flags[insn->op] & IR_OP_FLAG_COMMUTATIVE) {
2091 if (IR_IS_SYM_CONST(op2_insn->op)) {
2139 if (!IR_IS_SYM_CONST(op2_insn->op)
2155 if (IR_IS_SYM_CONST(op2_insn->op)) {
2179 if (IR_IS_SYM_CONST(op2_insn->op)) {
2219 if (IR_IS_SYM_CONST(op2_insn->op)) {
2233 if (IR_IS_SYM_CONST(op2_insn->op)) {
2247 if (IR_IS_SYM_CONST(op2_insn->op)) {
2258 if (IR_IS_SYM_CONST(op2_insn->op)) {
2284 if (IR_IS_SYM_CONST(op2_insn->op)) {
2314 if (func->op == IR_FUNC && func->proto) {
2332 return insn->op;
2343 if (!IR_IS_SYM_CONST(val->op)) {
2360 && (ctx->ir_base[insn->op3].op == IR_ADD_OV ||
2361 ctx->ir_base[insn->op3].op == IR_SUB_OV)))) {
2368 …if (((rule & IR_RULE_MASK) == IR_BINOP_INT && op_insn->op != IR_MUL) || rule == IR_LEA_OB || rule …
2370 && ctx->ir_base[op_insn->op1].op == load_op
2381 } else if ((ir_op_flags[op_insn->op] & IR_OP_FLAG_COMMUTATIVE)
2383 && ctx->ir_base[op_insn->op2].op == load_op
2394 && ctx->ir_base[op_insn->op1].op == load_op
2404 && ctx->ir_base[op_insn->op1].op == load_op
2414 && ctx->ir_base[op_insn->op1].op == load_op
2424 && ctx->ir_base[op_insn->op1].op == load_op
2434 && ctx->ir_base[op_insn->op1].op == load_op
2444 && ctx->ir_base[op_insn->op1].op == load_op
2454 && ctx->ir_base[op_insn->op1].op == load_op
2462 } else if (rule == IR_OP_INT && op_insn->op != IR_BSWAP) {
2464 && ctx->ir_base[op_insn->op1].op == load_op
2514 if (op_insn->op == IR_ADD ||
2515 op_insn->op == IR_SUB ||
2516 // op_insn->op == IR_MUL ||
2517 op_insn->op == IR_OR ||
2518 op_insn->op == IR_AND ||
2519 op_insn->op == IR_XOR) {
2521 && ctx->ir_base[op_insn->op1].op == IR_RLOAD
2528 } else if ((ir_op_flags[op_insn->op] & IR_OP_FLAG_COMMUTATIVE)
2530 && ctx->ir_base[op_insn->op2].op == IR_RLOAD
2553 return IR_SKIPPED | insn->op;
2565 if (op2_insn->op >= IR_EQ && op2_insn->op <= IR_UGT) {
2568 && !IR_IS_SYM_CONST(ctx->ir_base[op2_insn->op2].op)
2573 if (op1_insn->op == IR_AND && ctx->use_lists[op2_insn->op1].count == 1) {
2580 ((op1_insn->op == IR_OR || op1_insn->op == IR_AND || op1_insn->op == IR_XOR) ||
2582 ((op1_insn->op == IR_ADD || op1_insn->op == IR_SUB) &&
2583 (op2_insn->op == IR_EQ || op2_insn->op == IR_NE)))) {
2585 if (ir_op_flags[op1_insn->op] & IR_OP_FLAG_COMMUTATIVE) {
2606 } else if (op2_insn->op == IR_AND) {
2611 } else if (op2_insn->op == IR_OVERFLOW && ir_in_same_block(ctx, insn->op2)) {
2620 if (op2_insn->op == IR_ADD ||
2621 op2_insn->op == IR_SUB ||
2622 // op2_insn->op == IR_MUL ||
2623 op2_insn->op == IR_OR ||
2624 op2_insn->op == IR_AND ||
2625 op2_insn->op == IR_XOR) {
2628 if (ir_op_flags[op2_insn->op] & IR_OP_FLAG_COMMUTATIVE) {
2644 if (store_insn->op == IR_STORE && store_insn->op3 == insn->op2) {
2647 if (op_insn->op == IR_ADD ||
2648 op_insn->op == IR_SUB ||
2649 // op_insn->op == IR_MUL ||
2650 op_insn->op == IR_OR ||
2651 op_insn->op == IR_AND ||
2652 op_insn->op == IR_XOR) {
2653 if (ctx->ir_base[op_insn->op1].op == IR_LOAD
2665 } else if ((ir_op_flags[op_insn->op] & IR_OP_FLAG_COMMUTATIVE)
2666 && ctx->ir_base[op_insn->op2].op == IR_LOAD
2693 if (op1_insn->op >= IR_EQ && op1_insn->op <= IR_UGT) {
2710 if (op2_insn->op >= IR_EQ && op2_insn->op <= IR_UGT
2714 && ctx->ir_base[ctx->prev_ref[ref]].op == IR_SNAPSHOT))) {
2717 && !IR_IS_SYM_CONST(ctx->ir_base[op2_insn->op2].op)
2722 if ((op1_insn->op == IR_OR || op1_insn->op == IR_AND || op1_insn->op == IR_XOR) ||
2724 ((op1_insn->op == IR_ADD || op1_insn->op == IR_SUB) &&
2725 (op2_insn->op == IR_EQ || op2_insn->op == IR_NE))) {
2726 if (ir_op_flags[op1_insn->op] & IR_OP_FLAG_COMMUTATIVE) {
2743 if (store_insn->op == IR_STORE && store_insn->op3 == op2_insn->op1) {
2746 if ((op_insn->op == IR_OR || op_insn->op == IR_AND || op_insn->op == IR_XOR) ||
2748 ((op_insn->op == IR_ADD || op_insn->op == IR_SUB) &&
2749 (op2_insn->op == IR_EQ || op2_insn->op == IR_NE))) {
2750 if (ctx->ir_base[op_insn->op1].op == IR_LOAD
2763 } else if ((ir_op_flags[op_insn->op] & IR_OP_FLAG_COMMUTATIVE)
2764 && ctx->ir_base[op_insn->op2].op == IR_LOAD
2789 ir_match_fuse_load_cmp_fp_br(ctx, op2_insn, ref, insn->op == IR_GUARD_NOT);
2793 } else if (op2_insn->op == IR_AND) { // TODO: OR, XOR. etc
2798 } else if (op2_insn->op == IR_OVERFLOW && ir_in_same_block(ctx, insn->op2)) {
2805 return insn->op;
2810 return insn->op;
2816 return insn->op;
2820 return insn->op | IR_MAY_REUSE;
2824 return insn->op | IR_MAY_REUSE;
2826 return insn->op;
2837 if ((ctx->ir_base[insn->op2].op == IR_ALLOCA) || (ctx->ir_base[insn->op2].op == IR_VADDR)) {
2842 if (use_insn->op == IR_VA_START || use_insn->op == IR_VA_END) {
2843 } else if (use_insn->op == IR_VA_COPY) {
2847 } else if (use_insn->op == IR_VA_ARG) {
2871 if (ctx->ir_base[*p].op != IR_VA_END) {
2881 return insn->op;
2942 IR_ASSERT(var_insn->op == IR_VAR);
3073 if (insn->op == IR_SYM || insn->op == IR_FUNC) {
3076 } else if (insn->op == IR_STR) {
3126 if (val_insn->op == IR_STR) {
3139 if (val_insn->op == IR_FUNC || val_insn->op == IR_SYM) {
3244 if (IR_IS_SYM_CONST(addr_insn->op)) {
3434 if (IR_IS_SYM_CONST(addr_insn->op)) {
3439 if (offset_insn->op == IR_SUB) {
3503 IR_ASSERT(load_insn->op == IR_LOAD);
3517 if (IR_IS_SYM_CONST(val_insn->op)) {
3533 if (insn->op == IR_SYM || insn->op == IR_FUNC) {
3536 } else if (insn->op == IR_STR) {
3783 switch (insn->op) {
3785 IR_ASSERT(0 && "NIY binary op");
3811 switch (insn->op) {
3813 IR_ASSERT(0 && "NIY binary op");
3844 switch (insn->op) {
3846 IR_ASSERT(0 && "NIY binary op");
3961 if (insn->op == IR_MIN) {
3968 IR_ASSERT(insn->op == IR_MAX);
4046 if (insn->op == IR_STORE) {
4049 IR_ASSERT(insn->op == IR_VSTORE);
4056 switch (op_insn->op) {
4058 IR_ASSERT(0 && "NIY binary op");
4082 switch (op_insn->op) {
4084 IR_ASSERT(0 && "NIY binary op");
4116 IR_ASSERT(insn->op == IR_RSTORE);
4122 switch (op_insn->op) {
4124 IR_ASSERT(0 && "NIY binary op");
4146 switch (op_insn->op) {
4148 IR_ASSERT(0 && "NIY binary op");
4178 IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[insn->op2].op));
4192 if (insn->op == IR_MUL) {
4200 } else if (insn->op == IR_DIV) {
4205 IR_ASSERT(insn->op == IR_MOD);
4240 IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[insn->op2].op));
4304 IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[insn->op2].op));
4361 IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[op_insn->op2].op));
4363 if (insn->op == IR_STORE) {
4366 IR_ASSERT(insn->op == IR_VSTORE);
4370 if (op_insn->op == IR_MUL) {
4373 } else if (op_insn->op == IR_DIV) {
4377 IR_ASSERT(op_insn->op == IR_MOD);
4420 switch (insn->op) {
4454 if (insn->op == IR_STORE) {
4457 IR_ASSERT(insn->op == IR_VSTORE);
4472 switch (op_insn->op) {
4503 IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[insn->op2].op));
4519 switch (insn->op) {
4553 IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[op_insn->op2].op));
4556 if (insn->op == IR_STORE) {
4559 IR_ASSERT(insn->op == IR_VSTORE);
4563 switch (op_insn->op) {
4610 } else if (insn->op == IR_NOT) {
4612 } else if (insn->op == IR_NEG) {
4615 IR_ASSERT(insn->op == IR_BSWAP);
4655 if (insn->op == IR_CTLZ) {
4662 } else if (insn->op == IR_CTTZ) {
4669 IR_ASSERT(insn->op == IR_CTPOP);
4675 if (insn->op == IR_CTLZ) {
4687 if (insn->op == IR_CTLZ) {
4694 } else if (insn->op == IR_CTTZ) {
4701 IR_ASSERT(insn->op == IR_CTPOP);
4707 if (insn->op == IR_CTLZ) {
4714 } else if (insn->op == IR_CTTZ) {
4721 IR_ASSERT(insn->op == IR_CTPOP);
4739 if (insn->op == IR_CTLZ) {
4746 } else if (insn->op == IR_CTTZ) {
4757 if (insn->op == IR_CTLZ) {
4764 } else if (insn->op == IR_CTTZ) {
4776 if (insn->op == IR_CTLZ) {
4783 } else if (insn->op == IR_CTTZ) {
4940 if (insn->op == IR_STORE) {
4943 IR_ASSERT(insn->op == IR_VSTORE);
4951 } else if (op_insn->op == IR_NOT) {
4954 IR_ASSERT(op_insn->op == IR_NEG);
5046 && (insn->op == IR_MUL || insn->op == IR_MUL_OV)) {
5050 if (insn->op == IR_MUL || insn->op == IR_MUL_OV) {
5114 if (insn->op == IR_MUL || insn->op == IR_MUL_OV || insn->op == IR_DIV) {
5126 IR_ASSERT(insn->op == IR_MOD);
5192 if (insn->op == IR_NEG) {
5224 IR_ASSERT(insn->op == IR_ABS);
5295 switch (insn->op) {
5297 IR_ASSERT(0 && "NIY binary op");
5320 switch (insn->op) {
5322 IR_ASSERT(0 && "NIY binary op");
5350 switch (insn->op) {
5352 IR_ASSERT(0 && "NIY binary op");
5402 switch (insn->op) {
5404 IR_ASSERT(0 && "NIY binary op");
5427 switch (insn->op) {
5429 IR_ASSERT(0 && "NIY binary op");
5457 switch (insn->op) {
5459 IR_ASSERT(0 && "NIY binary op");
5493 …} else if (IR_IS_CONST_REF(op2) && !IR_IS_SYM_CONST(ctx->ir_base[op2].op) && ctx->ir_base[op2].val…
5549 static void _ir_emit_setcc_int(ir_ctx *ctx, uint8_t op, ir_reg def_reg)
5554 switch (op) {
5556 IR_ASSERT(0 && "NIY binary op");
5590 static void _ir_emit_setcc_int_mem(ir_ctx *ctx, uint8_t op, ir_mem mem)
5596 switch (op) {
5598 IR_ASSERT(0 && "NIY binary op");
5637 ir_op op = insn->op;
5655 …if (IR_IS_CONST_REF(op2) && !IR_IS_SYM_CONST(ctx->ir_base[op2].op) && ctx->ir_base[op2].val.u64 ==…
5656 if (op == IR_ULT) {
5663 } else if (op == IR_UGE) {
5670 } else if (op == IR_ULE) {
5671 op = IR_EQ;
5672 } else if (op == IR_UGT) {
5673 op = IR_NE;
5677 _ir_emit_setcc_int(ctx, op, def_reg);
5683 static void ir_emit_test_int_common(ir_ctx *ctx, ir_ref root, ir_ref ref, ir_op op)
5694 IR_ASSERT(binop_insn->op == IR_AND);
5711 … if ((op == IR_EQ || op == IR_NE) && val == 0xff && (sizeof(void*) == 8 || op1_reg <= IR_REG_R3)) {
5713 } else if ((op == IR_EQ || op == IR_NE) && val == 0xff00 && op1_reg <= IR_REG_R3) {
5725 } else if ((op == IR_EQ || op == IR_NE) && val == 0xffff) {
5727 } else if ((op == IR_EQ || op == IR_NE) && val == -1) {
5773 ir_emit_test_int_common(ctx, def, insn->op1, insn->op);
5774 _ir_emit_setcc_int(ctx, insn->op, def_reg);
5785 _ir_emit_setcc_int(ctx, insn->op, def_reg);
5796 ir_op op = cmp_insn->op;
5805 if (op1_reg == IR_REG_NONE && op2_reg != IR_REG_NONE && (op == IR_EQ || op == IR_NE)) {
5842 return op;
5849 ir_op op = ir_emit_cmp_fp_common(ctx, def, def, insn);
5854 switch (op) {
5856 IR_ASSERT(0 && "NIY binary op");
5929 …(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_t next_block, uint8_t op, bool int_cmp)
5938 if (int_cmp || op == IR_EQ || op == IR_NE) {
5939 op ^= 1; // reverse
5941 op ^= 5; // reverse
5950 switch (op) {
5952 IR_ASSERT(0 && "NIY binary op");
5985 switch (op) {
5987 IR_ASSERT(0 && "NIY binary op");
6052 ir_op op = cmp_insn->op;
6069 …if (IR_IS_CONST_REF(op2) && !IR_IS_SYM_CONST(ctx->ir_base[op2].op) && ctx->ir_base[op2].val.u64 ==…
6070 if (op == IR_ULT) {
6074 } else if (op == IR_UGE) {
6078 } else if (op == IR_ULE) {
6079 op = IR_EQ;
6080 } else if (op == IR_UGT) {
6081 op = IR_NE;
6087 if (prev_insn->op == IR_IF_TRUE || prev_insn->op == IR_IF_FALSE) {
6099 ir_emit_jcc(ctx, b, def, insn, next_block, op, 1);
6105 ir_op op = ctx->ir_base[op2].op;
6107 if (op >= IR_EQ && op <= IR_UGT) {
6110 IR_ASSERT(op == IR_AND);
6111 op = IR_NE;
6114 ir_emit_test_int_common(ctx, def, op2, op);
6115 ir_emit_jcc(ctx, b, def, insn, next_block, op, 1);
6120 ir_op op = ir_emit_cmp_fp_common(ctx, def, insn->op2, &ctx->ir_base[insn->op2]);
6121 ir_emit_jcc(ctx, b, def, insn, next_block, op, 0);
6233 } else if (IR_IS_CONST_REF(op2) && !IR_IS_SYM_CONST(ctx->ir_base[op2].op)) {
6243 if (IR_IS_CONST_REF(op3) && !IR_IS_SYM_CONST(ctx->ir_base[op3].op)) {
6314 ir_op op;
6329 op = ctx->ir_base[insn->op1].op;
6336 op ^= 1; // reverse
6346 } else if (IR_IS_CONST_REF(op2) && !IR_IS_SYM_CONST(ctx->ir_base[op2].op)) {
6355 if (IR_IS_CONST_REF(op3) && !IR_IS_SYM_CONST(ctx->ir_base[op3].op)) {
6362 op ^= 1; // reverse
6365 switch (op) {
6367 IR_ASSERT(0 && "NIY binary op");
6400 switch (op) {
6402 IR_ASSERT(0 && "NIY binary op");
6478 ir_op op;
6492 op = ir_emit_cmp_fp_common(ctx, def, insn->op1, &ctx->ir_base[insn->op1]);
6494 switch (op) {
6496 IR_ASSERT(0 && "NIY binary op");
6928 IR_ASSERT(!IR_IS_SYM_CONST(_insn->op));
7466 IR_ASSERT(var_insn->op == IR_VAR);
7489 IR_ASSERT(var_insn->op == IR_VAR);
7518 IR_ASSERT(var_insn->op == IR_VAR);
7667 ir_op op = cmp_insn->op;
7700 _ir_emit_setcc_int_mem(ctx, op, mem);
7825 IR_ASSERT(!IR_IS_SYM_CONST(val->op));
7879 IR_ASSERT(!IR_IS_SYM_CONST(val->op));
8254 if (use_insn->op == IR_CASE_VAL) {
8256 IR_ASSERT(!IR_IS_SYM_CONST(val->op));
8268 IR_ASSERT(use_insn->op == IR_CASE_DEFAULT);
8290 if (use_insn->op == IR_CASE_VAL) {
8292 IR_ASSERT(!IR_IS_SYM_CONST(val->op));
8399 if (insn->op == IR_IJMP && IR_IS_CONST_REF(insn->op2)) {
8401 if (prev != bb->start && ctx->ir_base[prev].op == IR_SNAPSHOT) {
8408 if (ctx->ir_base[bb->start].op != IR_CASE_DEFAULT) {
8426 if (use_insn->op == IR_CASE_VAL) {
8428 IR_ASSERT(!IR_IS_SYM_CONST(val->op));
8536 if (insn->op == IR_CALL
8547 && insn->op == IR_TAILCALL
8997 static bool ir_emit_guard_jcc(ir_ctx *ctx, uint32_t b, ir_ref def, uint32_t next_block, uint8_t op,…
9003 if (next_insn->op == IR_END || next_insn->op == IR_LOOP_END) {
9021 switch (op) {
9023 IR_ASSERT(0 && "NIY binary op");
9056 switch (op) {
9058 IR_ASSERT(0 && "NIY binary op");
9087 } else if (next_insn->op == IR_IJMP && IR_IS_CONST_REF(next_insn->op2)) {
9092 switch (op) {
9094 IR_ASSERT(0 && "NIY binary op");
9127 switch (op) {
9129 IR_ASSERT(0 && "NIY binary op");
9160 switch (op) {
9162 IR_ASSERT(0 && "NIY binary op");
9195 switch (op) {
9197 IR_ASSERT(0 && "NIY binary op");
9244 if ((insn->op == IR_GUARD && !is_true) || (insn->op == IR_GUARD_NOT && is_true)) {
9281 ir_op op;
9283 if (insn->op == IR_GUARD) {
9284 op = IR_EQ;
9286 op = IR_NE;
9288 return ir_emit_guard_jcc(ctx, b, def, next_block, op, addr, 1);
9291 if (insn->op == IR_GUARD) {
9315 ir_op op = cmp_insn->op;
9335 …if (IR_IS_CONST_REF(op2) && !IR_IS_SYM_CONST(ctx->ir_base[op2].op) && ctx->ir_base[op2].val.u64 ==…
9336 if (op == IR_ULT) {
9351 } else if (op == IR_UGE) {
9354 } else if (op == IR_ULE) {
9355 op = IR_EQ;
9356 } else if (op == IR_UGT) {
9357 op = IR_NE;
9362 if (insn->op == IR_GUARD) {
9363 op ^= 1; // reverse
9366 return ir_emit_guard_jcc(ctx, b, def, next_block, op, addr, 1);
9371 ir_op op = ir_emit_cmp_fp_common(ctx, def, insn->op2, &ctx->ir_base[insn->op2]);
9374 if (insn->op == IR_GUARD) {
9375 op ^= 1; // reverse
9377 return ir_emit_guard_jcc(ctx, b, def, next_block, op, addr, 0);
9383 ir_op op = (insn->op == IR_GUARD) ? IR_EQ : IR_NE;
9385 ir_emit_test_int_common(ctx, def, insn->op2, op);
9386 return ir_emit_guard_jcc(ctx, b, def, next_block, op, addr, 1);
9392 ir_op op = ctx->ir_base[insn->op2].op;
9394 if (insn->op == IR_GUARD) {
9395 op ^= 1; // reverse
9397 return ir_emit_guard_jcc(ctx, b, def, next_block, op, addr, 1);
9411 if (insn->op == IR_GUARD) {
9417 if (insn->op == IR_GUARD) {
9745 if (insn->op == IR_PARAM) {
9873 if (insn->op == IR_PARAM) {
9960 switch (ctx->rules ? *rule : insn->op) {
9995 if (insn->op == IR_VLOAD
9999 } else if (insn->op != IR_PARAM) {
10013 if (insn->op == IR_PARAM && reg == IR_REG_NONE) {
10018 } else if (insn->op == IR_PARAM) {
10022 } else if (insn->op == IR_VAR) {
10034 if (use_insn->op == IR_VLOAD) {
10045 } else if (use_insn->op == IR_VSTORE) {
10062 insn_flags = ir_op_flags[insn->op];
10133 if (insn->op == IR_CALL) {
10481 ir_op op = ctx->ir_base[insn->op2].op;
10483 if (op == IR_ADD ||
10484 op == IR_SUB ||
10485 // op == IR_MUL ||
10486 op == IR_OR ||
10487 op == IR_AND ||
10488 op == IR_XOR) {
10489 op = IR_NE;
10491 IR_ASSERT(op >= IR_EQ && op <= IR_UGT);
10493 ir_emit_jcc(ctx, b, i, insn, _ir_next_block(ctx, _b), op, 1);
10738 } else if (insn->op == IR_STR) {
