Lines Matching refs:def
3687 static void ir_emit_binop_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
3694 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
3695 ir_reg op1_reg = ctx->regs[def][1];
3696 ir_reg op2_reg = ctx->regs[def][2];
3779 mem = ir_fuse_load(ctx, def, op2);
3809 if (IR_REG_SPILLED(ctx->regs[def][0])) {
3810 ir_emit_store(ctx, type, def, def_reg);
3814 static void ir_emit_imul3(ir_ctx *ctx, ir_ref def, ir_insn *insn)
3821 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
3822 ir_reg op1_reg = ctx->regs[def][1];
3852 mem = ir_fuse_load(ctx, def, op1);
3858 if (IR_REG_SPILLED(ctx->regs[def][0])) {
3859 ir_emit_store(ctx, type, def, def_reg);
3863 static void ir_emit_min_max_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
3870 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
3871 ir_reg op1_reg = ctx->regs[def][1];
3872 ir_reg op2_reg = ctx->regs[def][2];
3915 if (IR_REG_SPILLED(ctx->regs[def][0])) {
3916 ir_emit_store(ctx, type, def, def_reg);
3920 static void ir_emit_overflow(ir_ctx *ctx, ir_ref def, ir_insn *insn)
3924 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
3934 if (IR_REG_SPILLED(ctx->regs[def][0])) {
3935 ir_emit_store(ctx, insn->type, def, def_reg);
3939 static void ir_emit_overflow_and_branch(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_…
3975 static void ir_emit_mem_binop_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
3986 mem = ir_fuse_mem(ctx, def, def, insn, ctx->regs[def][2]);
4045 static void ir_emit_reg_binop_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4107 static void ir_emit_mul_div_mod_pwr2(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4113 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
4114 ir_reg op1_reg = ctx->regs[def][1];
4148 || if (ir_type_size[type] == 8 && ctx->regs[def][2] != IR_REG_NONE) {
4149 || ir_reg op2_reg = ctx->regs[def][2];
4161 if (IR_REG_SPILLED(ctx->regs[def][0])) {
4162 ir_emit_store(ctx, type, def, def_reg);
4166 static void ir_emit_sdiv_pwr2(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4172 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
4173 ir_reg op1_reg = ctx->regs[def][1];
4204 || ir_reg op2_reg = ctx->regs[def][2];
4224 if (IR_REG_SPILLED(ctx->regs[def][0])) {
4225 ir_emit_store(ctx, type, def, def_reg);
4229 static void ir_emit_smod_pwr2(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4235 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
4236 ir_reg op1_reg = ctx->regs[def][1];
4237 ir_reg tmp_reg = ctx->regs[def][3];
4271 || if (ir_type_size[type] == 8 && ctx->regs[def][2] != IR_REG_NONE) {
4272 || ir_reg op2_reg = ctx->regs[def][2];
4286 if (IR_REG_SPILLED(ctx->regs[def][0])) {
4287 ir_emit_store(ctx, type, def, def_reg);
4291 static void ir_emit_mem_mul_div_mod_pwr2(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4303 mem = ir_fuse_mem(ctx, def, def, insn, ctx->regs[def][2]);
4323 static void ir_emit_shift(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4328 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
4329 ir_reg op1_reg = ctx->regs[def][1];
4330 ir_reg op2_reg = ctx->regs[def][2];
4378 if (IR_REG_SPILLED(ctx->regs[def][0])) {
4379 ir_emit_store(ctx, type, def, def_reg);
4383 static void ir_emit_mem_shift(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4394 mem = ir_fuse_mem(ctx, def, def, insn, ctx->regs[def][2]);
4432 static void ir_emit_shift_const(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4439 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
4440 ir_reg op1_reg = ctx->regs[def][1];
4477 if (IR_REG_SPILLED(ctx->regs[def][0])) {
4478 ir_emit_store(ctx, type, def, def_reg);
4482 static void ir_emit_mem_shift_const(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4496 mem = ir_fuse_mem(ctx, def, def, insn, ctx->regs[def][2]);
4523 static void ir_emit_op_int(ir_ctx *ctx, ir_ref def, ir_insn *insn, uint32_t rule)
4529 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
4530 ir_reg op1_reg = ctx->regs[def][1];
4569 if (IR_REG_SPILLED(ctx->regs[def][0])) {
4570 ir_emit_store(ctx, type, def, def_reg);
4574 static void ir_emit_bit_count(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4580 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
4581 ir_reg op1_reg = ctx->regs[def][1];
4670 mem = ir_fuse_load(ctx, def, op1);
4736 if (IR_REG_SPILLED(ctx->regs[def][0])) {
4737 ir_emit_store(ctx, type, def, def_reg);
4741 static void ir_emit_ctpop(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4747 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
4748 ir_reg op1_reg = ctx->regs[def][1];
4749 ir_reg tmp_reg = ctx->regs[def][2];
4751 || ir_reg const_reg = ctx->regs[def][3];
4866 if (IR_REG_SPILLED(ctx->regs[def][0])) {
4867 ir_emit_store(ctx, type, def, def_reg);
4871 static void ir_emit_mem_op_int(ir_ctx *ctx, ir_ref def, ir_insn *insn, uint32_t rule)
4880 mem = ir_fuse_mem(ctx, def, def, insn, ctx->regs[def][2]);
4898 static void ir_emit_abs_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4904 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
4905 ir_reg op1_reg = ctx->regs[def][1];
4919 if (IR_REG_SPILLED(ctx->regs[def][0])) {
4920 ir_emit_store(ctx, type, def, def_reg);
4924 static void ir_emit_bool_not_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4930 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
4931 ir_reg op1_reg = ctx->regs[def][1];
4949 if (IR_REG_SPILLED(ctx->regs[def][0])) {
4950 ir_emit_store(ctx, type, def, def_reg);
4954 static void ir_emit_mul_div_mod(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4961 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
4962 ir_reg op1_reg = ctx->regs[def][1];
4963 ir_reg op2_reg = ctx->regs[def][2];
4995 mem = ir_fuse_load(ctx, def, op2);
5006 mem = ir_fuse_load(ctx, def, op2);
5028 mem = ir_fuse_load(ctx, def, op2);
5044 mem = ir_fuse_load(ctx, def, op2);
5058 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5059 ir_emit_store(ctx, type, def, def_reg);
5062 ir_emit_store(ctx, type, def, IR_REG_RAX);
5072 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5073 ir_emit_store(ctx, type, def, def_reg);
5077 int32_t offset = ir_ref_spill_slot_offset(ctx, def, &fp);
5087 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5088 ir_emit_store(ctx, type, def, def_reg);
5091 ir_emit_store(ctx, type, def, IR_REG_RDX);
5109 static void ir_emit_op_fp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
5115 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
5116 ir_reg op1_reg = ctx->regs[def][1];
5195 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5196 ir_emit_store(ctx, insn->type, def, def_reg);
5200 static void ir_emit_binop_sse2(ir_ctx *ctx, ir_ref def, ir_insn *insn)
5207 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
5208 ir_reg op1_reg = ctx->regs[def][1];
5209 ir_reg op2_reg = ctx->regs[def][2];
5285 mem = ir_fuse_load(ctx, def, op2);
5312 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5313 ir_emit_store(ctx, insn->type, def, def_reg);
5317 static void ir_emit_binop_avx(ir_ctx *ctx, ir_ref def, ir_insn *insn)
5324 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
5325 ir_reg op1_reg = ctx->regs[def][1];
5326 ir_reg op2_reg = ctx->regs[def][2];
5392 mem = ir_fuse_load(ctx, def, op2);
5419 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5420 ir_emit_store(ctx, insn->type, def, def_reg);
5571 static void ir_emit_cmp_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
5579 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
5580 ir_reg op1_reg = ctx->regs[def][1];
5581 ir_reg op2_reg = ctx->regs[def][2];
5598 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5599 ir_emit_store(ctx, insn->type, def, def_reg);
5605 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5606 ir_emit_store(ctx, insn->type, def, def_reg);
5615 ir_emit_cmp_int_common(ctx, type, def, insn, op1_reg, op1, op2_reg, op2);
5617 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5618 ir_emit_store(ctx, insn->type, def, def_reg);
5707 static void ir_emit_testcc_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
5709 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
5712 ir_emit_test_int_common(ctx, def, insn->op1, insn->op);
5714 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5715 ir_emit_store(ctx, insn->type, def, def_reg);
5719 static void ir_emit_setcc_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
5721 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
5725 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5726 ir_emit_store(ctx, insn->type, def, def_reg);
5784 static void ir_emit_cmp_fp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
5788 ir_op op = ir_emit_cmp_fp_common(ctx, def, def, insn);
5789 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
5790 ir_reg tmp_reg = ctx->regs[def][3];
5839 if (IR_REG_SPILLED(ctx->regs[def][0])) {
5840 ir_emit_store(ctx, insn->type, def, def_reg);
5844 static void ir_emit_jmp_true(ir_ctx *ctx, uint32_t b, ir_ref def, uint32_t next_block)
5856 static void ir_emit_jmp_false(ir_ctx *ctx, uint32_t b, ir_ref def, uint32_t next_block)
5868 static void ir_emit_jcc(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_t next_block, ui…
5988 static void ir_emit_cmp_and_branch_int(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_t…
6011 ir_emit_jmp_false(ctx, b, def, next_block);
6015 ir_emit_jmp_true(ctx, b, def, next_block);
6036 ir_emit_cmp_int_common(ctx, type, def, cmp_insn, op1_reg, op1, op2_reg, op2);
6038 ir_emit_jcc(ctx, b, def, insn, next_block, op, 1);
6041 static void ir_emit_test_and_branch_int(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_…
6053 ir_emit_test_int_common(ctx, def, op2, op);
6054 ir_emit_jcc(ctx, b, def, insn, next_block, op, 1);
6057 static void ir_emit_cmp_and_branch_fp(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_t …
6059 ir_op op = ir_emit_cmp_fp_common(ctx, def, insn->op2, &ctx->ir_base[insn->op2]);
6060 ir_emit_jcc(ctx, b, def, insn, next_block, op, 0);
6063 static void ir_emit_if_int(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_t next_block)
6066 ir_reg op2_reg = ctx->regs[def][2];
6102 mem = ir_fuse_load(ctx, def, insn->op2);
6108 ir_emit_jcc(ctx, b, def, insn, next_block, IR_NE, 1);
6111 static void ir_emit_cond(ir_ctx *ctx, ir_ref def, ir_insn *insn)
6120 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
6121 ir_reg op1_reg = ctx->regs[def][1];
6122 ir_reg op2_reg = ctx->regs[def][2];
6123 ir_reg op3_reg = ctx->regs[def][3];
6176 ir_emit_load_ex(ctx, type, def_reg, op2, def);
6186 ir_emit_load_ex(ctx, type, def_reg, op3, def);
6191 if (IR_REG_SPILLED(ctx->regs[def][0])) {
6192 ir_emit_store(ctx, type, def, def_reg);
6221 ir_emit_load_ex(ctx, type, def_reg, op2, def);
6234 ir_emit_load_ex(ctx, type, def_reg, op3, def);
6238 if (IR_REG_SPILLED(ctx->regs[def][0])) {
6239 ir_emit_store(ctx, type, def, def_reg);
6243 static void ir_emit_cond_cmp_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
6250 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
6251 ir_reg op2_reg = ctx->regs[def][2];
6252 ir_reg op3_reg = ctx->regs[def][3];
6267 ir_emit_cmp_int_common2(ctx, def, insn->op1, &ctx->ir_base[insn->op1]);
6289 ir_emit_load_ex(ctx, type, def_reg, op2, def);
6298 ir_emit_load_ex(ctx, type, def_reg, op3, def);
6384 ir_emit_load_ex(ctx, type, def_reg, op2, def);
6397 ir_emit_load_ex(ctx, type, def_reg, op3, def);
6402 if (IR_REG_SPILLED(ctx->regs[def][0])) {
6403 ir_emit_store(ctx, type, def, def_reg);
6407 static void ir_emit_cond_cmp_fp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
6414 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
6415 ir_reg op2_reg = ctx->regs[def][2];
6416 ir_reg op3_reg = ctx->regs[def][3];
6431 op = ir_emit_cmp_fp_common(ctx, def, insn->op1, &ctx->ir_base[insn->op1]);
6484 ir_emit_load_ex(ctx, type, def_reg, op2, def);
6497 ir_emit_load_ex(ctx, type, def_reg, op3, def);
6501 if (IR_REG_SPILLED(ctx->regs[def][0])) {
6502 ir_emit_store(ctx, type, def, def_reg);
6585 static void ir_emit_sext(ir_ctx *ctx, ir_ref def, ir_insn *insn)
6591 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
6592 ir_reg op1_reg = ctx->regs[def][1];
6640 mem = ir_fuse_load(ctx, def, insn->op1);
6676 if (IR_REG_SPILLED(ctx->regs[def][0])) {
6677 ir_emit_store(ctx, dst_type, def, def_reg);
6681 static void ir_emit_zext(ir_ctx *ctx, ir_ref def, ir_insn *insn)
6687 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
6688 ir_reg op1_reg = ctx->regs[def][1];
6739 mem = ir_fuse_load(ctx, def, insn->op1);
6774 if (IR_REG_SPILLED(ctx->regs[def][0])) {
6775 ir_emit_store(ctx, dst_type, def, def_reg);
6779 static void ir_emit_trunc(ir_ctx *ctx, ir_ref def, ir_insn *insn)
6783 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
6784 ir_reg op1_reg = ctx->regs[def][1];
6799 ir_emit_load_ex(ctx, dst_type, def_reg, insn->op1, def);
6801 if (IR_REG_SPILLED(ctx->regs[def][0])) {
6802 ir_emit_store(ctx, dst_type, def, def_reg);
6806 static void ir_emit_bitcast(ir_ctx *ctx, ir_ref def, ir_insn *insn)
6812 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
6813 ir_reg op1_reg = ctx->regs[def][1];
6827 ir_emit_load_ex(ctx, dst_type, def_reg, insn->op1, def);
6839 ir_emit_load_ex(ctx, dst_type, def_reg, insn->op1, def);
6881 mem = ir_fuse_load(ctx, def, insn->op1);
6928 mem = ir_fuse_load(ctx, def, insn->op1);
6936 if (IR_REG_SPILLED(ctx->regs[def][0])) {
6937 ir_emit_store(ctx, dst_type, def, def_reg);
6941 static void ir_emit_int2fp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
6947 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
6948 ir_reg op1_reg = ctx->regs[def][1];
7047 mem = ir_fuse_load(ctx, def, insn->op1);
7095 if (IR_REG_SPILLED(ctx->regs[def][0])) {
7096 ir_emit_store(ctx, dst_type, def, def_reg);
7100 static void ir_emit_fp2int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7106 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
7107 ir_reg op1_reg = ctx->regs[def][1];
7197 mem = ir_fuse_load(ctx, def, insn->op1);
7237 if (IR_REG_SPILLED(ctx->regs[def][0])) {
7238 ir_emit_store(ctx, dst_type, def, def_reg);
7242 static void ir_emit_fp2fp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7248 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
7249 ir_reg op1_reg = ctx->regs[def][1];
7298 mem = ir_fuse_load(ctx, def, insn->op1);
7318 if (IR_REG_SPILLED(ctx->regs[def][0])) {
7319 ir_emit_store(ctx, dst_type, def, def_reg);
7323 static void ir_emit_copy_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7326 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
7327 ir_reg op1_reg = ctx->regs[def][1];
7341 ir_emit_store(ctx, type, def, op1_reg);
7345 if (def_reg != IR_REG_NONE && IR_REG_SPILLED(ctx->regs[def][0])) {
7346 ir_emit_store(ctx, type, def, def_reg);
7350 static void ir_emit_copy_fp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7353 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
7354 ir_reg op1_reg = ctx->regs[def][1];
7368 ir_emit_store(ctx, type, def, op1_reg);
7372 if (def_reg != IR_REG_NONE && IR_REG_SPILLED(ctx->regs[def][0])) {
7373 ir_emit_store(ctx, type, def, def_reg);
7377 static void ir_emit_vaddr(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7382 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
7392 if (IR_REG_SPILLED(ctx->regs[def][0])) {
7393 ir_emit_store(ctx, type, def, def_reg);
7397 static void ir_emit_vload(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7401 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
7408 if (def_reg == IR_REG_NONE && ir_is_same_mem_var(ctx, def, var_insn->op3)) {
7414 if (IR_REG_SPILLED(ctx->regs[def][0])) {
7415 ir_emit_store(ctx, type, def, def_reg);
7478 static void ir_emit_load_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7481 ir_reg op2_reg = ctx->regs[def][2];
7482 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
7485 if (ctx->use_lists[def].count == 1) {
7501 mem = ir_fuse_addr(ctx, def, insn->op2);
7502 if (IR_REG_SPILLED(ctx->regs[def][0]) && ir_is_same_spill_slot(ctx, def, mem)) {
7503 if (!ir_may_avoid_spill_load(ctx, def, def)) {
7512 if (IR_REG_SPILLED(ctx->regs[def][0])) {
7513 ir_emit_store(ctx, type, def, def_reg);
7517 static void ir_emit_load_fp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7520 ir_reg op2_reg = ctx->regs[def][2];
7521 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
7524 if (ctx->use_lists[def].count == 1) {
7540 mem = ir_fuse_addr(ctx, def, insn->op2);
7541 if (IR_REG_SPILLED(ctx->regs[def][0]) && ir_is_same_spill_slot(ctx, def, mem)) {
7542 if (!ir_may_avoid_spill_load(ctx, def, def)) {
7551 if (IR_REG_SPILLED(ctx->regs[def][0])) {
7552 ir_emit_store(ctx, type, def, def_reg);
7687 static void ir_emit_rload(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7693 if (ctx->vregs[def]
7694 && ctx->live_intervals[ctx->vregs[def]]
7695 && ctx->live_intervals[ctx->vregs[def]]->stack_spill_pos != -1) {
7696 ir_emit_store(ctx, type, def, src_reg);
7699 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
7705 if (!insn->op3 || !ir_is_same_spill_slot(ctx, def, IR_MEM_BO(ctx->spill_base, insn->op3))) {
7706 ir_emit_store(ctx, type, def, src_reg);
7717 if (IR_REG_SPILLED(ctx->regs[def][0])
7718 && (!insn->op3 || !ir_is_same_spill_slot(ctx, def, IR_MEM_BO(ctx->spill_base, insn->op3)))) {
7719 ir_emit_store(ctx, type, def, def_reg);
7749 static void ir_emit_alloca(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7753 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
7755 if (ctx->use_lists[def].count == 1) {
7776 ir_reg op2_reg = ctx->regs[def][2];
7800 if (IR_REG_SPILLED(ctx->regs[def][0])) {
7801 ir_emit_store(ctx, insn->type, def, def_reg);
7804 ir_emit_store(ctx, IR_ADDR, def, IR_REG_STACK_POINTER);
7808 static void ir_emit_afree(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7830 ir_reg op2_reg = ctx->regs[def][2];
7845 static void ir_emit_block_begin(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7849 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
7853 if (IR_REG_SPILLED(ctx->regs[def][0])) {
7854 ir_emit_store(ctx, IR_ADDR, def, def_reg);
7858 static void ir_emit_block_end(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7862 ir_reg op2_reg = ctx->regs[def][2];
7873 static void ir_emit_frame_addr(ir_ctx *ctx, ir_ref def)
7877 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
7884 if (IR_REG_SPILLED(ctx->regs[def][0])) {
7885 ir_emit_store(ctx, IR_ADDR, def, def_reg);
7889 static void ir_emit_va_start(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7896 ir_reg op2_reg = ctx->regs[def][2];
7897 ir_reg tmp_reg = ctx->regs[def][3];
7929 ir_reg op2_reg = ctx->regs[def][2];
7930 ir_reg tmp_reg = ctx->regs[def][3];
7991 static void ir_emit_va_copy(ir_ctx *ctx, ir_ref def, ir_insn *insn)
7996 ir_reg tmp_reg = ctx->regs[def][1];
7997 ir_reg op2_reg = ctx->regs[def][2];
7998 ir_reg op3_reg = ctx->regs[def][3];
8030 ir_reg tmp_reg = ctx->regs[def][1];
8031 ir_reg op2_reg = ctx->regs[def][2];
8032 ir_reg op3_reg = ctx->regs[def][3];
8072 static void ir_emit_va_arg(ir_ctx *ctx, ir_ref def, ir_insn *insn)
8078 ir_reg def_reg = ctx->regs[def][0];
8079 ir_reg op2_reg = ctx->regs[def][2];
8080 ir_reg tmp_reg = ctx->regs[def][3];
8099 if (IR_REG_SPILLED(ctx->regs[def][0])) {
8100 ir_emit_store(ctx, type, def, def_reg);
8107 ir_reg def_reg = ctx->regs[def][0];
8108 ir_reg op2_reg = ctx->regs[def][2];
8109 ir_reg tmp_reg = ctx->regs[def][3];
8154 if (IR_REG_SPILLED(ctx->regs[def][0])) {
8155 ir_emit_store(ctx, type, def, def_reg);
8163 static void ir_emit_switch(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn)
8175 ir_reg op2_reg = ctx->regs[def][2];
8176 ir_reg tmp_reg = ctx->regs[def][3];
8435 static int32_t ir_emit_arguments(ir_ctx *ctx, ir_ref def, ir_insn *insn, ir_reg tmp_reg)
8512 src_reg = ir_get_alocated_reg(ctx, def, j);
8580 src_reg = ir_get_alocated_reg(ctx, def, j);
8709 static void ir_emit_call_ex(ir_ctx *ctx, ir_ref def, ir_insn *insn, int32_t used_stack)
8738 ir_reg op2_reg = ctx->regs[def][2];
8750 mem = ir_fuse_load(ctx, def, insn->op2);
8775 def_reg = IR_REG_NUM(ctx->regs[def][0]);
8780 if (IR_REG_SPILLED(ctx->regs[def][0])) {
8781 ir_emit_store(ctx, insn->type, def, def_reg);
8783 } else if (ctx->use_lists[def].count > 1) {
8784 ir_emit_store(ctx, insn->type, def, IR_REG_INT_RET1);
8788 def_reg = IR_REG_NUM(ctx->regs[def][0]);
8794 if (IR_REG_SPILLED(ctx->regs[def][0])) {
8795 ir_emit_store(ctx, insn->type, def, def_reg);
8797 } else if (ctx->use_lists[def].count > 1) {
8798 ir_emit_store(ctx, insn->type, def, IR_REG_FP_RET1);
8801 if (ctx->use_lists[def].count > 1) {
8806 offset = ir_ref_spill_slot_offset(ctx, def, &fp);
8825 if (IR_REG_SPILLED(ctx->regs[def][0])) {
8826 ir_emit_store(ctx, insn->type, def, def_reg);
8835 static void ir_emit_call(ir_ctx *ctx, ir_ref def, ir_insn *insn)
8837 int32_t used_stack = ir_emit_arguments(ctx, def, insn, ctx->regs[def][1]);
8838 ir_emit_call_ex(ctx, def, insn, used_stack);
8841 static void ir_emit_tailcall(ir_ctx *ctx, ir_ref def, ir_insn *insn)
8845 int32_t used_stack = ir_emit_arguments(ctx, def, insn, ctx->regs[def][1]);
8848 ir_emit_call_ex(ctx, def, insn, used_stack);
8878 ir_reg op2_reg = ctx->regs[def][2];
8890 mem = ir_fuse_load(ctx, def, insn->op2);
8899 static void ir_emit_ijmp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
8903 ir_reg op2_reg = ctx->regs[def][2];
8921 ir_mem mem = ir_fuse_load(ctx, def, insn->op2);
8936 static bool ir_emit_guard_jcc(ir_ctx *ctx, uint32_t b, ir_ref def, uint32_t next_block, uint8_t op,…
8940 ir_insn *next_insn = &ctx->ir_base[def + 1];
9171 static bool ir_emit_guard(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_t next_block)
9175 ir_reg op2_reg = ctx->regs[def][2];
9211 mem = ir_fuse_load(ctx, def, insn->op2);
9227 return ir_emit_guard_jcc(ctx, b, def, next_block, op, addr, 1);
9249 static bool ir_emit_guard_cmp_int(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_t next…
9299 ir_emit_cmp_int_common(ctx, type, def, cmp_insn, op1_reg, op1, op2_reg, op2);
9305 return ir_emit_guard_jcc(ctx, b, def, next_block, op, addr, 1);
9308 static bool ir_emit_guard_cmp_fp(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_t next_…
9310 ir_op op = ir_emit_cmp_fp_common(ctx, def, insn->op2, &ctx->ir_base[insn->op2]);
9316 return ir_emit_guard_jcc(ctx, b, def, next_block, op, addr, 0);
9319 static bool ir_emit_guard_test_int(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_t nex…
9324 ir_emit_test_int_common(ctx, def, insn->op2, op);
9325 return ir_emit_guard_jcc(ctx, b, def, next_block, op, addr, 1);
9328 static bool ir_emit_guard_jcc_int(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_t next…
9336 return ir_emit_guard_jcc(ctx, b, def, next_block, op, addr, 1);
9339 static bool ir_emit_guard_overflow(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn)
9365 static void ir_emit_lea(ir_ctx *ctx, ir_ref def, ir_type type)
9369 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
9370 ir_mem mem = ir_fuse_addr(ctx, def, def);
9406 if (IR_REG_SPILLED(ctx->regs[def][0])) {
9407 ir_emit_store(ctx, type, def, def_reg);
9411 static void ir_emit_tls(ir_ctx *ctx, ir_ref def, ir_insn *insn)
9415 ir_reg reg = IR_REG_NUM(ctx->regs[def][0]);
9417 if (ctx->use_lists[def].count == 1) {
9459 if (IR_REG_SPILLED(ctx->regs[def][0])) {
9460 ir_emit_store(ctx, IR_ADDR, def, reg);
9464 static void ir_emit_sse_sqrt(ir_ctx *ctx, ir_ref def, ir_insn *insn)
9468 ir_reg op3_reg = ctx->regs[def][3];
9469 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
9481 if (IR_REG_SPILLED(ctx->regs[def][0])) {
9482 ir_emit_store(ctx, insn->type, def, def_reg);
9486 static void ir_emit_sse_round(ir_ctx *ctx, ir_ref def, ir_insn *insn, int round_op)
9490 ir_reg op3_reg = ctx->regs[def][3];
9491 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
9507 if (IR_REG_SPILLED(ctx->regs[def][0])) {
9508 ir_emit_store(ctx, insn->type, def, def_reg);
9512 static void ir_emit_exitcall(ir_ctx *ctx, ir_ref def, ir_insn *insn)
9516 ir_reg def_reg = IR_REG_NUM(ctx->regs[def][0]);
9616 if (IR_REG_SPILLED(ctx->regs[def][0])) {
9617 ir_emit_store(ctx, insn->type, def, def_reg);
