Lines Matching refs:reg
35 bool ir_reg_is_int(int32_t reg) in ir_reg_is_int() argument
37 IR_ASSERT(reg >= 0 && reg < IR_REG_NUM); in ir_reg_is_int()
38 return reg >= IR_REG_GP_FIRST && reg <= IR_REG_GP_LAST; in ir_reg_is_int()
123 ival->reg = IR_REG_NONE; in ir_new_live_range()
225 static void ir_add_fixed_live_range(ir_ctx *ctx, ir_reg reg, ir_live_pos start, ir_live_pos end) in ir_add_fixed_live_range() argument
227 int v = ctx->vregs_count + 1 + reg; in ir_add_fixed_live_range()
234 ival->reg = reg; in ir_add_fixed_live_range()
272 ival->reg = IR_REG_NONE; in ir_add_tmp()
507 ir_reg reg; in ir_add_fusion_ranges() local
523 ir_add_fixed_live_range(ctx, constraints.tmp_regs[n].reg, in ir_add_fusion_ranges()
550 reg = (j < constraints.hints_count) ? constraints.hints[j] : IR_REG_NONE; in ir_add_fusion_ranges()
552 if (EXPECTED(reg == IR_REG_NONE)) { in ir_add_fusion_ranges()
565 ir_add_use(ctx, ival, j, use_pos, reg, use_flags, -input); in ir_add_fusion_ranges()
741 ir_add_fixed_live_range(ctx, constraints.tmp_regs[n].reg, in ir_compute_live_ranges()
760 ir_reg reg = constraints.def_reg; in ir_compute_live_ranges() local
762 if (reg != IR_REG_NONE) { in ir_compute_live_ranges()
766 ir_add_fixed_live_range(ctx, reg, IR_START_LIVE_POS_FROM_REF(bb->start), def_pos); in ir_compute_live_ranges()
791 ir_add_use(ctx, ival, 0, def_pos, reg, def_flags, hint_ref); in ir_compute_live_ranges()
817 ir_reg reg = (j < constraints.hints_count) ? constraints.hints[j] : IR_REG_NONE; in ir_compute_live_ranges() local
826 if (reg != IR_REG_NONE) { in ir_compute_live_ranges()
828 ir_add_fixed_live_range(ctx, reg, use_pos, use_pos + IR_USE_SUB_REF); in ir_compute_live_ranges()
847 ir_add_use(ctx, ival, j, use_pos, reg, IR_USE_FLAGS(def_flags, j), hint_ref); in ir_compute_live_ranges()
855 } else if (reg != IR_REG_NONE) { in ir_compute_live_ranges()
857 ir_add_fixed_live_range(ctx, reg, use_pos, use_pos + IR_USE_SUB_REF); in ir_compute_live_ranges()
1163 ir_reg reg; in ir_add_fusion_ranges() local
1180 ir_add_fixed_live_range(ctx, constraints.tmp_regs[n].reg, in ir_add_fusion_ranges()
1207 reg = (j < constraints.hints_count) ? constraints.hints[j] : IR_REG_NONE; in ir_add_fusion_ranges()
1209 if (EXPECTED(reg == IR_REG_NONE)) { in ir_add_fusion_ranges()
1223 ir_add_use(ctx, ival, j, use_pos, reg, use_flags, -input); in ir_add_fusion_ranges()
1359 ir_add_fixed_live_range(ctx, constraints.tmp_regs[n].reg, in ir_compute_live_ranges()
1376 ir_reg reg = constraints.def_reg; in ir_compute_live_ranges() local
1378 if (reg != IR_REG_NONE) { in ir_compute_live_ranges()
1382 ir_add_fixed_live_range(ctx, reg, IR_START_LIVE_POS_FROM_REF(bb->start), def_pos); in ir_compute_live_ranges()
1409 ir_add_use(ctx, ival, 0, def_pos, reg, def_flags, hint_ref); in ir_compute_live_ranges()
1433 ir_reg reg = (j < constraints.hints_count) ? constraints.hints[j] : IR_REG_NONE; in ir_compute_live_ranges() local
1442 if (reg != IR_REG_NONE) { in ir_compute_live_ranges()
1444 ir_add_fixed_live_range(ctx, reg, use_pos, use_pos + IR_USE_SUB_REF); in ir_compute_live_ranges()
1467 ir_add_use(ctx, ival, j, use_pos, reg, IR_USE_FLAGS(def_flags, j), hint_ref); in ir_compute_live_ranges()
1475 if (reg != IR_REG_NONE) { in ir_compute_live_ranges()
1477 ir_add_fixed_live_range(ctx, reg, use_pos, use_pos + IR_USE_SUB_REF); in ir_compute_live_ranges()
1481 } else if (reg != IR_REG_NONE) { in ir_compute_live_ranges()
1483 ir_add_fixed_live_range(ctx, reg, use_pos, use_pos + IR_USE_SUB_REF); in ir_compute_live_ranges()
2246 ir_reg_name(_ival->reg, _ival->type)); \
2272 ir_reg_name(_ival->reg, _ival->type), \
2468 child->reg = IR_REG_NONE; in ir_split_interval_at()
2641 ir_reg reg; in ir_get_first_reg_hint() local
2645 reg = use_pos->hint; in ir_get_first_reg_hint()
2646 if (reg >= 0 && IR_REGSET_IN(available, reg)) { in ir_get_first_reg_hint()
2647 return reg; in ir_get_first_reg_hint()
2658 ir_reg reg; in ir_try_allocate_preferred_reg() local
2663 reg = use_pos->hint; in ir_try_allocate_preferred_reg()
2664 if (reg >= 0 && IR_REGSET_IN(available, reg)) { in ir_try_allocate_preferred_reg()
2665 if (ival->end <= freeUntilPos[reg]) { in ir_try_allocate_preferred_reg()
2667 return reg; in ir_try_allocate_preferred_reg()
2678 reg = ctx->live_intervals[ctx->vregs[use_pos->hint_ref]]->reg; in ir_try_allocate_preferred_reg()
2679 if (reg >= 0 && IR_REGSET_IN(available, reg)) { in ir_try_allocate_preferred_reg()
2680 if (ival->end <= freeUntilPos[reg]) { in ir_try_allocate_preferred_reg()
2682 return reg; in ir_try_allocate_preferred_reg()
2696 ir_reg reg; in ir_get_preferred_reg() local
2700 reg = use_pos->hint; in ir_get_preferred_reg()
2701 if (reg >= 0 && IR_REGSET_IN(available, reg)) { in ir_get_preferred_reg()
2702 return reg; in ir_get_preferred_reg()
2704 reg = ctx->live_intervals[ctx->vregs[use_pos->hint_ref]]->reg; in ir_get_preferred_reg()
2705 if (reg >= 0 && IR_REGSET_IN(available, reg)) { in ir_get_preferred_reg()
2706 return reg; in ir_get_preferred_reg()
2808 int i, reg; in ir_try_allocate_free_reg() local
2844 reg = other->reg; in ir_try_allocate_free_reg()
2845 IR_ASSERT(reg >= 0); in ir_try_allocate_free_reg()
2846 if (reg >= IR_REG_SCRATCH) { in ir_try_allocate_free_reg()
2847 if (reg == IR_REG_SCRATCH) { in ir_try_allocate_free_reg()
2850 IR_ASSERT(reg == IR_REG_ALL); in ir_try_allocate_free_reg()
2854 IR_REGSET_EXCL(available, reg); in ir_try_allocate_free_reg()
2872 reg = other->reg; in ir_try_allocate_free_reg()
2873 IR_ASSERT(reg >= 0); in ir_try_allocate_free_reg()
2874 if (reg >= IR_REG_SCRATCH) { in ir_try_allocate_free_reg()
2877 if (reg == IR_REG_SCRATCH) { in ir_try_allocate_free_reg()
2880 IR_ASSERT(reg == IR_REG_ALL); in ir_try_allocate_free_reg()
2884 IR_REGSET_FOREACH(regset, reg) { in ir_try_allocate_free_reg()
2885 if (next < freeUntilPos[reg]) { in ir_try_allocate_free_reg()
2886 freeUntilPos[reg] = next; in ir_try_allocate_free_reg()
2889 } else if (IR_REGSET_IN(available, reg)) { in ir_try_allocate_free_reg()
2890 IR_REGSET_INCL(overlapped, reg); in ir_try_allocate_free_reg()
2891 if (next < freeUntilPos[reg]) { in ir_try_allocate_free_reg()
2892 freeUntilPos[reg] = next; in ir_try_allocate_free_reg()
2905 reg = ir_try_allocate_preferred_reg(ctx, ival, available, freeUntilPos); in ir_try_allocate_free_reg()
2906 if (reg != IR_REG_NONE) { in ir_try_allocate_free_reg()
2907 ival->reg = reg; in ir_try_allocate_free_reg()
2913 return reg; in ir_try_allocate_free_reg()
2919 reg = ctx->live_intervals[ival->vreg]->reg; in ir_try_allocate_free_reg()
2920 if (reg >= 0 && IR_REGSET_IN(available, reg)) { in ir_try_allocate_free_reg()
2921 ival->reg = reg; in ir_try_allocate_free_reg()
2927 return reg; in ir_try_allocate_free_reg()
2941 reg = ir_get_first_reg_hint(ctx, other, non_conflicting); in ir_try_allocate_free_reg()
2943 if (reg >= 0) { in ir_try_allocate_free_reg()
2944 IR_REGSET_EXCL(non_conflicting, reg); in ir_try_allocate_free_reg()
2953 reg = IR_REGSET_FIRST(non_conflicting); in ir_try_allocate_free_reg()
2955 reg = IR_REGSET_FIRST(scratch); in ir_try_allocate_free_reg()
2958 reg = IR_REGSET_FIRST(scratch); in ir_try_allocate_free_reg()
2961 reg = IR_REGSET_FIRST(available); in ir_try_allocate_free_reg()
2963 ival->reg = reg; in ir_try_allocate_free_reg()
2969 return reg; in ir_try_allocate_free_reg()
2973 reg = IR_REG_NONE; in ir_try_allocate_free_reg()
2978 reg = i; in ir_try_allocate_free_reg()
2980 && !IR_REGSET_IN(IR_REGSET_SCRATCH, reg) in ir_try_allocate_free_reg()
2984 reg = i; in ir_try_allocate_free_reg()
3000 ival->reg = pref_reg; in ir_try_allocate_free_reg()
3002 ival->reg = reg; in ir_try_allocate_free_reg()
3005 ival->reg = reg; in ir_try_allocate_free_reg()
3014 return reg; in ir_try_allocate_free_reg()
3024 int i, reg; in ir_allocate_blocked_reg() local
3085 reg = other->reg; in ir_allocate_blocked_reg()
3086 IR_ASSERT(reg >= 0); in ir_allocate_blocked_reg()
3087 if (reg >= IR_REG_SCRATCH) { in ir_allocate_blocked_reg()
3090 if (reg == IR_REG_SCRATCH) { in ir_allocate_blocked_reg()
3093 IR_ASSERT(reg == IR_REG_ALL); in ir_allocate_blocked_reg()
3096 IR_REGSET_FOREACH(regset, reg) { in ir_allocate_blocked_reg()
3097 blockPos[reg] = nextUsePos[reg] = 0; in ir_allocate_blocked_reg()
3099 } else if (IR_REGSET_IN(available, reg)) { in ir_allocate_blocked_reg()
3101 blockPos[reg] = nextUsePos[reg] = 0; in ir_allocate_blocked_reg()
3105 if (pos < nextUsePos[reg]) { in ir_allocate_blocked_reg()
3106 nextUsePos[reg] = pos; in ir_allocate_blocked_reg()
3117 reg = other->reg; in ir_allocate_blocked_reg()
3118 IR_ASSERT(reg >= 0); in ir_allocate_blocked_reg()
3119 if (reg >= IR_REG_SCRATCH) { in ir_allocate_blocked_reg()
3125 if (reg == IR_REG_SCRATCH) { in ir_allocate_blocked_reg()
3128 IR_ASSERT(reg == IR_REG_ALL); in ir_allocate_blocked_reg()
3131 IR_REGSET_FOREACH(regset, reg) { in ir_allocate_blocked_reg()
3132 if (overlap < nextUsePos[reg]) { in ir_allocate_blocked_reg()
3133 nextUsePos[reg] = overlap; in ir_allocate_blocked_reg()
3135 if (overlap < blockPos[reg]) { in ir_allocate_blocked_reg()
3136 blockPos[reg] = overlap; in ir_allocate_blocked_reg()
3140 } else if (IR_REGSET_IN(available, reg)) { in ir_allocate_blocked_reg()
3145 if (overlap < nextUsePos[reg]) { in ir_allocate_blocked_reg()
3146 nextUsePos[reg] = overlap; in ir_allocate_blocked_reg()
3148 if (overlap < blockPos[reg]) { in ir_allocate_blocked_reg()
3149 blockPos[reg] = overlap; in ir_allocate_blocked_reg()
3154 if (pos < nextUsePos[reg]) { in ir_allocate_blocked_reg()
3155 nextUsePos[reg] = pos; in ir_allocate_blocked_reg()
3164 reg = IR_REG_NONE; in ir_allocate_blocked_reg()
3166 reg = ir_get_preferred_reg(ctx, ival, available); in ir_allocate_blocked_reg()
3168 if (reg == IR_REG_NONE) { in ir_allocate_blocked_reg()
3170 reg = IR_REGSET_FIRST(available); in ir_allocate_blocked_reg()
3174 pos = nextUsePos[reg]; in ir_allocate_blocked_reg()
3176 IR_REGSET_EXCL(tmp_regset, reg); in ir_allocate_blocked_reg()
3180 reg = i; in ir_allocate_blocked_reg()
3210 if (ival->end > blockPos[reg]) { in ir_allocate_blocked_reg()
3214 ir_live_pos split_pos = ir_last_use_pos_before(ival, blockPos[reg] + 1, in ir_allocate_blocked_reg()
3217 split_pos = ir_first_use_pos_after(ival, blockPos[reg], in ir_allocate_blocked_reg()
3224 if (split_pos >= blockPos[reg]) { in ir_allocate_blocked_reg()
3226 IR_REGSET_EXCL(available, reg); in ir_allocate_blocked_reg()
3235 split_pos = ir_find_optimal_split_position(ctx, ival, split_pos, blockPos[reg], 1); in ir_allocate_blocked_reg()
3247 if (reg == other->reg) { in ir_allocate_blocked_reg()
3289 other->reg = IR_REG_NONE; in ir_allocate_blocked_reg()
3324 if (reg == other->reg) { in ir_allocate_blocked_reg()
3344 ival->reg = reg; in ir_allocate_blocked_reg()
3351 return reg; in ir_allocate_blocked_reg()
3465 && (ival->next || ival->reg == IR_REG_NONE)) { in ir_assign_bound_spill_slots()
3487 ir_reg reg; in ir_linear_scan() local
3667 reg = ir_try_allocate_free_reg(ctx, ival, &active, inactive, &unhandled); in ir_linear_scan()
3668 if (reg == IR_REG_NONE) { in ir_linear_scan()
3669 reg = ir_allocate_blocked_reg(ctx, ival, &active, &inactive, &unhandled); in ir_linear_scan()
3698 && (ival->next || ival->reg == IR_REG_NONE) in ir_linear_scan()
3850 static void ir_set_fused_reg(ir_ctx *ctx, ir_ref root, ir_ref ref_and_op, int8_t reg) in ir_set_fused_reg() argument
3854 IR_ASSERT(reg != IR_REG_NONE); in ir_set_fused_reg()
3861 ir_strtab_lookup(ctx->fused_regs, key, 8, 0x10000000 | reg); in ir_set_fused_reg()
3869 int8_t reg, old_reg; in assign_regs() local
3883 if (ival->reg != IR_REG_NONE) { in assign_regs()
3884 reg = ival->reg; in assign_regs()
3885 IR_REGSET_INCL(used_regs, reg); in assign_regs()
3889 ir_set_alocated_reg(ctx, ref, use_pos->op_num, reg); in assign_regs()
3905 if (ival->reg != IR_REG_NONE) { in assign_regs()
3906 IR_REGSET_INCL(used_regs, ival->reg); in assign_regs()
3909 reg = ival->reg; in assign_regs()
3914 ir_set_alocated_reg(ctx, ref, use_pos->op_num, reg); in assign_regs()
3923 if (ival->reg != IR_REG_NONE) { in assign_regs()
3927 IR_REGSET_INCL(used_regs, ival->reg); in assign_regs()
3930 reg = ival->reg; in assign_regs()
3940 ir_set_alocated_reg(ctx, ref, use_pos->op_num, reg); in assign_regs()
3948 reg = IR_REG_NONE; in assign_regs()
3953 reg = IR_REG_NONE; in assign_regs()
3961 reg |= IR_REG_SPILL_SPECIAL; in assign_regs()
3963 reg |= IR_REG_SPILL_STORE; in assign_regs()
3970 && use_pos->hint != reg in assign_regs()
3976 reg = IR_REG_NONE; in assign_regs()
3985 ir_set_alocated_reg(ctx, ref, use_pos->op_num, reg); in assign_regs()
3990 reg |= IR_REG_SPILL_SPECIAL; in assign_regs()
3992 reg |= IR_REG_SPILL_LOAD; in assign_regs()
4006 reg |= IR_REG_SPILL_SPECIAL; in assign_regs()
4008 reg |= IR_REG_SPILL_LOAD; in assign_regs()
4010 if (reg != old_reg) { in assign_regs()
4013 ir_set_fused_reg(ctx, ref, -use_pos->hint_ref * sizeof(ir_ref) + use_pos->op_num, reg); in assign_regs()
4024 reg = IR_REG_NONE; in assign_regs()
4028 if (reg != old_reg) { in assign_regs()
4031 ir_set_fused_reg(ctx, ref, -use_pos->hint_ref * sizeof(ir_ref) + use_pos->op_num, reg); in assign_regs()
4041 ir_set_alocated_reg(ctx, ref, use_pos->op_num, reg); in assign_regs()
4052 reg = IR_REG_SPILL_STORE | IR_REG_STACK_POINTER; in assign_regs()
4053 ir_set_alocated_reg(ctx, ref, use_pos->op_num, reg); in assign_regs()
4070 IR_ASSERT(ival->reg != IR_REG_NONE); in assign_regs()
4071 IR_REGSET_INCL(used_regs, ival->reg); in assign_regs()
4072 reg = ival->reg; in assign_regs()
4080 reg |= IR_REG_SPILL_LOAD; in assign_regs()
4084 reg |= IR_REG_SPILL_LOAD; in assign_regs()
4088 ir_set_alocated_reg(ctx, ival->tmp_ref, ival->tmp_op_num, reg); in assign_regs()
