Lines Matching refs:insn
41 IR_ALWAYS_INLINE void _ir_add_predecessors(const ir_insn *insn, ir_worklist *worklist) in _ir_add_predecessors() argument
46 if (insn->op == IR_MERGE || insn->op == IR_LOOP_BEGIN) { in _ir_add_predecessors()
47 n = insn->inputs_count; in _ir_add_predecessors()
48 for (p = insn->ops + 1; n > 0; p++, n--) { in _ir_add_predecessors()
53 } else if (insn->op != IR_START) { in _ir_add_predecessors()
54 if (EXPECTED(insn->op1)) { in _ir_add_predecessors()
55 ir_worklist_push(worklist, insn->op1); in _ir_add_predecessors()
64 ir_insn *insn; in ir_build_cfg() local
89 insn = &ctx->ir_base[ref]; in ir_build_cfg()
91 if (insn->op == IR_NOP) { in ir_build_cfg()
94 IR_ASSERT(IR_IS_BB_END(insn->op)); in ir_build_cfg()
100 if (n > 1 || (n == 1 && (ir_op_flags[insn->op] & IR_OP_FLAG_TERMINATOR) != 0)) { in ir_build_cfg()
107 ref = insn->op1; in ir_build_cfg()
109 insn = &ctx->ir_base[ref]; in ir_build_cfg()
110 if (IR_IS_BB_START(insn->op)) { in ir_build_cfg()
113 ref = insn->op1; // follow connected control blocks untill BB start in ir_build_cfg()
120 _ir_add_predecessors(insn, &worklist); in ir_build_cfg()
138 insn = &ctx->ir_base[ref]; in ir_build_cfg()
140 if (insn->op == IR_NOP) { in ir_build_cfg()
143 IR_ASSERT(IR_IS_BB_START(insn->op)); in ir_build_cfg()
153 insn = &ctx->ir_base[next]; in ir_build_cfg()
154 if ((ir_op_flags[insn->op] & IR_OP_FLAG_CONTROL) && insn->op1 == ref) { in ir_build_cfg()
160 if (IR_IS_BB_END(insn->op)) { in ir_build_cfg()
183 insn = &ctx->ir_base[start]; in ir_build_cfg()
184 if (insn->op == IR_NOP) { in ir_build_cfg()
191 IR_ASSERT(IR_IS_BB_START(insn->op)); in ir_build_cfg()
205 if (insn->op == IR_START) { in ir_build_cfg()
210 if (insn->op == IR_MERGE || insn->op == IR_LOOP_BEGIN) { in ir_build_cfg()
211 n = insn->inputs_count; in ir_build_cfg()
215 } else if (EXPECTED(insn->op1)) { in ir_build_cfg()
216 if (insn->op == IR_ENTRY) { in ir_build_cfg()
224 IR_ASSERT(insn->op == IR_BEGIN); /* start of unreachable block */ in ir_build_cfg()
239 insn = &ctx->ir_base[bb->start]; in ir_build_cfg()
242 n = insn->inputs_count; in ir_build_cfg()
243 for (p = insn->ops + 1; n > 0; p++, q++, n--) { in ir_build_cfg()
253 ref = insn->op1; in ir_build_cfg()
255 IR_ASSERT(IR_OPND_KIND(ir_op_flags[insn->op], 1) == IR_OPND_CONTROL); in ir_build_cfg()
325 ir_insn *insn = &ctx->ir_base[merge]; in ir_remove_merge_input() local
327 IR_ASSERT(insn->op == IR_MERGE || insn->op == IR_LOOP_BEGIN); in ir_remove_merge_input()
328 n = insn->inputs_count; in ir_remove_merge_input()
332 ir_ref input = ir_insn_op(insn, j); in ir_remove_merge_input()
336 ir_insn_set_op(insn, i, input); in ir_remove_merge_input()
344 insn->op = IR_BEGIN; in ir_remove_merge_input()
345 insn->inputs_count = 1; in ir_remove_merge_input()
371 insn->inputs_count = i; in ir_remove_merge_input()
426 ir_insn *insn = &ctx->ir_base[ref]; in ir_remove_unreachable_blocks() local
428 IR_ASSERT(ir_op_flags[insn->op] & IR_OP_FLAG_TERMINATOR); in ir_remove_unreachable_blocks()
432 ctx->ir_base[1].op1 = insn->op3; in ir_remove_unreachable_blocks()
436 ctx->ir_base[prev].op3 = insn->op3; in ir_remove_unreachable_blocks()
473 ir_insn *insn = &ctx->ir_base[bb->start]; in ir_remove_unreachable_blocks() local
480 IR_ASSERT(n == insn->inputs_count); in ir_remove_unreachable_blocks()
481 for (p = insn->ops + 1; n > 0; p++, q++, n--) { in ir_remove_unreachable_blocks()
490 ref = insn->op1; in ir_remove_unreachable_blocks()
492 IR_ASSERT(IR_OPND_KIND(ir_op_flags[insn->op], 1) == IR_OPND_CONTROL); in ir_remove_unreachable_blocks()
1477 ir_insn *insn = &ctx->ir_base[successor_bb->start]; in ir_schedule_blocks_bottom_up() local
1479 if (insn->op == IR_CASE_DEFAULT) { in ir_schedule_blocks_bottom_up()
1480 prob = insn->op2; in ir_schedule_blocks_bottom_up()
1484 } else if (insn->op == IR_CASE_VAL) { in ir_schedule_blocks_bottom_up()
1485 prob = insn->op3; in ir_schedule_blocks_bottom_up()
1489 } else if (insn->op == IR_ENTRY) { in ir_schedule_blocks_bottom_up()
1678 ir_insn *insn; in ir_schedule_blocks_top_down() local
1728 insn = &ctx->ir_base[successor_bb->start]; in ir_schedule_blocks_top_down()
1729 if (insn->op == IR_IF_TRUE || insn->op == IR_IF_FALSE) { in ir_schedule_blocks_top_down()
1730 prob = insn->op2; in ir_schedule_blocks_top_down()
1737 } else if (insn->op == IR_CASE_DEFAULT) { in ir_schedule_blocks_top_down()
1738 prob = insn->op2; in ir_schedule_blocks_top_down()
1742 } else if (insn->op == IR_CASE_VAL) { in ir_schedule_blocks_top_down()
1743 prob = insn->op3; in ir_schedule_blocks_top_down()
1747 } else if (insn->op == IR_ENTRY) { in ir_schedule_blocks_top_down()
1810 ir_insn *insn = &ctx->ir_base[ref]; in ir_schedule_blocks() local
1812 if (insn->op == IR_UNREACHABLE && ctx->ir_base[insn->op1].op != IR_TAILCALL) { in ir_schedule_blocks()
1843 ref = insn->op3; in ir_schedule_blocks()
