Lines Matching refs:reg
189 |.macro ASM_REG_IMM_OP, op, type, reg, val
191 | op Rx(reg), #val
193 | op Rw(reg), #val
197 |.macro ASM_FP_REG_IMM_OP, op, type, reg, val
199 | op Rd(reg-IR_REG_FP_FIRST), #val
202 | op Rs(reg-IR_REG_FP_FIRST), #val
265 const char *ir_reg_name(int8_t reg, ir_type type)
267 if (reg >= IR_REG_NUM) {
268 if (reg == IR_REG_SCRATCH) {
271 IR_ASSERT(reg == IR_REG_ALL);
275 IR_ASSERT(reg >= 0 && reg < IR_REG_NUM);
277 type = (reg < IR_REG_FP_FIRST) ? IR_ADDR : IR_DOUBLE;
280 return _ir_reg_name[reg];
282 return _ir_reg_name32[reg];
1110 static int32_t ir_ref_spill_slot_offset(ir_ctx *ctx, ir_ref ref, ir_reg *reg)
1119 *reg = ctx->spill_base;
1122 *reg = (ctx->flags & IR_USE_FRAME_POINTER) ? IR_REG_FRAME_POINTER : IR_REG_STACK_POINTER;
1154 static int32_t ir_var_spill_slot(ir_ctx *ctx, ir_ref ref, ir_reg *reg)
1159 *reg = (ctx->flags & IR_USE_FRAME_POINTER) ? IR_REG_FRAME_POINTER : IR_REG_STACK_POINTER;
1182 static void ir_emit_load_imm_int(ir_ctx *ctx, ir_type type, ir_reg reg, int64_t val)
1190 if (reg != IR_REG_ZR) {
1191 | mov Rx(reg), xzr
1194 | movz Rx(reg), #((uint64_t)(val))
1196 | movn Rx(reg), #(~((uint64_t)(val)))
1198 | movz Rx(reg), #((uint64_t)(val) & 0xffff)
1200 | movk Rx(reg), #(((uint64_t)(val) >> 16) & 0xffff), lsl #16
1203 | movk Rx(reg), #(((uint64_t)(val) >> 32) & 0xffff), lsl #32
1206 | movk Rx(reg), #(((uint64_t)(val) >> 48) & 0xffff), lsl #48
1209 | movz Rx(reg), #(((uint64_t)(val) >> 16) & 0xffff), lsl #16
1211 | movk Rx(reg), #(((uint64_t)(val) >> 32) & 0xffff), lsl #32
1214 | movk Rx(reg), #(((uint64_t)(val) >> 48) & 0xffff), lsl #48
1217 | movz Rx(reg), #(((uint64_t)(val) >> 32) & 0xffff), lsl #32
1219 | movk Rx(reg), #(((uint64_t)(val) >> 48) & 0xffff), lsl #48
1222 | movz Rx(reg), #(((uint64_t)(val) >> 48) & 0xffff), lsl #48
1226 if (reg != IR_REG_ZR) {
1227 | mov Rw(reg), wzr
1230 | movz Rw(reg), #((uint64_t)(val))
1232 | movn Rw(reg), #(~((uint64_t)(val)))
1234 | movz Rw(reg), #((uint64_t)(val) & 0xffff)
1236 | movk Rw(reg), #(((uint64_t)(val) >> 16) & 0xffff), lsl #16
1239 | movz Rw(reg), #(((uint64_t)(val) >> 16) & 0xffff), lsl #16
1244 static void ir_emit_load_mem_int(ir_ctx *ctx, ir_type type, ir_reg reg, ir_mem mem)
1258 | ldr Rx(reg), [Rx(base_reg), #offset]
1261 | ldr Rw(reg), [Rx(base_reg), #offset]
1265 | ldrsh Rw(reg), [Rx(base_reg), #offset]
1267 | ldrh Rw(reg), [Rx(base_reg), #offset]
1272 | ldrsb Rw(reg), [Rx(base_reg), #offset]
1274 | ldrb Rw(reg), [Rx(base_reg), #offset]
1292 | ldr Rx(reg), [Rx(base_reg), Rx(index_reg)]
1295 | ldr Rw(reg), [Rx(base_reg), Rx(index_reg)]
1299 | ldrsh Rw(reg), [Rx(base_reg), Rx(index_reg)]
1301 | ldrh Rw(reg), [Rx(base_reg), Rx(index_reg)]
1306 | ldrsb Rw(reg), [Rx(base_reg), Rx(index_reg)]
1308 | ldrb Rw(reg), [Rx(base_reg), Rx(index_reg)]
1314 static void ir_emit_load_imm_fp(ir_ctx *ctx, ir_type type, ir_reg reg, ir_ref src)
1322 | fmov Rs(reg-IR_REG_FP_FIRST), wzr
1324 | fmov Rd(reg-IR_REG_FP_FIRST), xzr
1328 | ldr Rd(reg-IR_REG_FP_FIRST), =>label
1331 | ldr Rs(reg-IR_REG_FP_FIRST), =>label
1336 static void ir_emit_load_mem_fp(ir_ctx *ctx, ir_type type, ir_reg reg, ir_mem mem)
1347 | ldr Rd(reg-IR_REG_FP_FIRST), [Rx(base_reg), #offset]
1350 | ldr Rs(reg-IR_REG_FP_FIRST), [Rx(base_reg), #offset]
1363 | ldr Rd(reg-IR_REG_FP_FIRST), [Rx(base_reg), Rx(index_reg)]
1366 | ldr Rs(reg-IR_REG_FP_FIRST), [Rx(base_reg), Rx(index_reg)]
1370 static void ir_emit_load_mem(ir_ctx *ctx, ir_type type, ir_reg reg, ir_mem mem)
1373 ir_emit_load_mem_int(ctx, type, reg, mem);
1375 ir_emit_load_mem_fp(ctx, type, reg, mem);
1379 static void ir_load_local_addr(ir_ctx *ctx, ir_reg reg, ir_ref src)
1388 | add Rx(reg), Rx(base), #offset
1396 static void ir_emit_load(ir_ctx *ctx, ir_type type, ir_reg reg, ir_ref src)
1405 ir_emit_load_imm_int(ctx, type, reg, (intptr_t)addr);
1411 | adr Rx(reg), =>label
1413 ir_emit_load_imm_int(ctx, type, reg, insn->val.i64);
1416 ir_emit_load_imm_fp(ctx, type, reg, src);
1420 ir_emit_load_mem(ctx, type, reg, mem);
1422 ir_load_local_addr(ctx, reg, src);
1426 static void ir_emit_store_mem_int(ir_ctx *ctx, ir_type type, ir_mem mem, ir_reg reg)
1440 | str Rx(reg), [Rx(base_reg), #offset]
1443 | str Rw(reg), [Rx(base_reg), #offset]
1446 | strh Rw(reg), [Rx(base_reg), #offset]
1449 | strb Rw(reg), [Rx(base_reg), #offset]
1466 | str Rx(reg), [Rx(base_reg), Rx(index_reg)]
1469 | str Rw(reg), [Rx(base_reg), Rx(index_reg)]
1472 | strh Rw(reg), [Rx(base_reg), Rx(index_reg)]
1475 | strb Rw(reg), [Rx(base_reg), Rx(index_reg)]
1480 static void ir_emit_store_mem_fp(ir_ctx *ctx, ir_type type, ir_mem mem, ir_reg reg)
1491 | str Rd(reg-IR_REG_FP_FIRST), [Rx(base_reg), #offset]
1494 | str Rs(reg-IR_REG_FP_FIRST), [Rx(base_reg), #offset]
1507 | str Rd(reg-IR_REG_FP_FIRST), [Rx(base_reg), Rx(index_reg)]
1510 | str Rs(reg-IR_REG_FP_FIRST), [Rx(base_reg), Rx(index_reg)]
1514 static void ir_emit_store_mem(ir_ctx *ctx, ir_type type, ir_mem mem, ir_reg reg)
1517 ir_emit_store_mem_int(ctx, type, mem, reg);
1519 ir_emit_store_mem_fp(ctx, type, mem, reg);
1523 static void ir_emit_store(ir_ctx *ctx, ir_type type, ir_ref dst, ir_reg reg)
1526 ir_emit_store_mem(ctx, type, ir_ref_spill_slot(ctx, dst), reg);
2075 ir_reg reg;
2078 reg = insn->op3;
2089 | ASM_REG_REG_IMM_OP add, type, reg, reg, val->i32
2092 | ASM_REG_REG_IMM_OP sub, type, reg, reg, val->i32
2095 | ASM_REG_REG_IMM_OP orr, type, reg, reg, val->i32
2098 | ASM_REG_REG_IMM_OP and, type, reg, reg, val->i32
2101 | ASM_REG_REG_IMM_OP eor, type, reg, reg, val->i32
2113 | ASM_REG_REG_REG_OP add, type, reg, reg, op2_reg
2116 | ASM_REG_REG_REG_OP sub, type, reg, reg, op2_reg
2119 | ASM_REG_REG_REG_OP mul, type, reg, reg, op2_reg
2122 | ASM_REG_REG_REG_OP orr, type, reg, reg, op2_reg
2125 | ASM_REG_REG_REG_OP and, type, reg, reg, op2_reg
2128 | ASM_REG_REG_REG_OP eor, type, reg, reg, op2_reg
2924 …void ir_emit_jz(ir_ctx *ctx, uint32_t b, uint32_t next_block, uint8_t op, ir_type type, ir_reg reg)
2942 | cbz Rx(reg), =>true_block
2944 | cbz Rw(reg), =>true_block
2949 | cbnz Rx(reg), =>true_block
2951 | cbnz Rw(reg), =>true_block
3666 /* same reg */
3693 /* same reg */
3779 ir_reg reg;
3786 reg = (ctx->flags & IR_USE_FRAME_POINTER) ? IR_REG_FRAME_POINTER : IR_REG_STACK_POINTER;
3789 return IR_MEM_BO(reg, offset);
3792 reg = ir_get_fused_reg(ctx, root, ref * sizeof(ir_ref) + 1);
3794 reg = ctx->regs[ref][1];
3796 if (IR_REG_SPILLED(reg)) {
3797 reg = IR_REG_NUM(reg);
3798 ir_emit_load(ctx, IR_ADDR, reg, addr_insn->op1);
3800 return IR_MEM_BO(reg, ctx->ir_base[addr_insn->op2].val.i32);
3804 reg = (ctx->flags & IR_USE_FRAME_POINTER) ? IR_REG_FRAME_POINTER : IR_REG_STACK_POINTER;
3806 return IR_MEM_BO(reg, offset);
5025 static void ir_emit_guard_jz(ir_ctx *ctx, uint8_t op, void *addr, ir_type type, ir_reg reg)
5032 | cbnz Rx(reg), &addr
5034 | cbnz Rw(reg), &addr
5039 | cbz Rx(reg), &addr
5041 | cbz Rw(reg), &addr
5226 ir_reg reg = IR_REG_NUM(ctx->regs[def][0]);
5234 || code = 0xd53bd060 | reg; // TODO: hard-coded: mrs reg, tpidrro_el0
5236 | and Rx(reg), Rx(reg), #0xfffffffffffffff8
5237 |//??? MEM_ACCESS_64_WITH_UOFFSET_64 ldr, Rx(reg), Rx(reg), #insn->op2, TMP1
5238 |//??? MEM_ACCESS_64_WITH_UOFFSET_64 ldr, Rx(reg), Rx(reg), #insn->op3, TMP1
5240 || code = 0xd53bd040 | reg; // TODO: hard-coded: mrs reg, tpidr_el0
5243 | ldr Rx(reg), [Rx(reg), #insn->op2]
5246 ir_emit_store(ctx, IR_ADDR, def, reg);
5505 && (ival->next || ival->reg == IR_REG_NONE)) {
5536 ir_reg reg;
5573 reg = constraints.def_reg;
5574 if (reg != IR_REG_NONE && IR_REGSET_IN(available, reg)) {
5575 IR_REGSET_EXCL(available, reg);
5576 ctx->regs[i][0] = reg | IR_REG_SPILL_STORE;
5583 reg = ir_get_free_reg(insn->type, available);
5584 IR_REGSET_EXCL(available, reg);
5585 ctx->regs[i][0] = reg | IR_REG_SPILL_STORE;
5593 ival->reg = IR_REG_NONE;
5596 if (insn->op == IR_PARAM && reg == IR_REG_NONE) {
5624 ival->reg = IR_REG_NONE;
5636 ival->reg = IR_REG_NONE;
5651 ir_reg reg = ir_get_free_reg(constraints.tmp_regs[n].type, available);
5653 IR_REGSET_EXCL(available, reg);
5657 reg |= IR_REG_SPILL_LOAD;
5659 ctx->regs[i][constraints.tmp_regs[n].num] = reg;
5660 } else if (constraints.tmp_regs[n].reg == IR_REG_SCRATCH) {
5663 IR_REGSET_EXCL(available, constraints.tmp_regs[n].reg);
5672 ir_reg reg = IR_REG_NUM(ctx->regs[i][0]);
5673 ctx->regs[i][1] = reg | IR_REG_SPILL_LOAD;
5676 ir_reg reg = (j < constraints.hints_count) ? constraints.hints[j] : IR_REG_NONE;
5678 if (reg != IR_REG_NONE && IR_REGSET_IN(available, reg)) {
5679 IR_REGSET_EXCL(available, reg);
5680 ctx->regs[i][j] = reg | IR_REG_SPILL_LOAD;
5684 reg = ir_get_free_reg(ctx->ir_base[input].type, available);
5685 IR_REGSET_EXCL(available, reg);
5686 ctx->regs[i][j] = reg | IR_REG_SPILL_LOAD;
5740 ir_reg reg;
5741 (void) reg;
5743 IR_REGSET_FOREACH(used_preserved_regs, reg) {
