Lines Matching refs:offset
33 #define IR_MEM_BO(base, offset) IR_MEM(base, offset, IR_REG_NONE, 0)
35 IR_ALWAYS_INLINE ir_mem IR_MEM(ir_reg base, int32_t offset, ir_reg index, int32_t shift)
40 IR_ASSERT(index == IR_REG_NONE || offset == 0);
47 ((uint64_t)(uint32_t)offset |
54 #define IR_SPILL_POS_TO_OFFSET(offset) \
56 ((offset) + (int32_t)sizeof(void*) * 2) : \
57 ((offset) + ctx->call_stack_size))
137 static bool aarch64_may_encode_imm7_addr_offset(const int64_t offset, uint32_t type_size)
139 return (uintptr_t)(offset) % type_size == 0
140 && offset < 63 * (int32_t)type_size
141 && offset >= -64 * (int32_t)type_size;
144 static bool aarch64_may_encode_addr_offset(int64_t offset, uint32_t type_size)
146 return (uintptr_t)(offset) % type_size == 0 && (uintptr_t)(offset) < 0xfff * type_size;
443 int64_t offset = ctx->ir_base[insn->op2].val.u64 - 1;
444 if (!aarch64_may_encode_imm12(offset)) {
1112 int32_t offset;
1115 offset = ctx->live_intervals[ctx->vregs[ref]]->stack_spill_pos;
1116 IR_ASSERT(offset != -1);
1120 return offset;
1123 return IR_SPILL_POS_TO_OFFSET(offset);
1128 int32_t offset;
1132 offset = ctx->live_intervals[v]->stack_spill_pos;
1133 IR_ASSERT(offset != -1);
1136 return IR_MEM_BO(ctx->spill_base, offset);
1139 offset = IR_SPILL_POS_TO_OFFSET(offset);
1140 return IR_MEM_BO(base, offset);
1250 int32_t offset = IR_MEM_OFFSET(mem);
1253 if (aarch64_may_encode_addr_offset(offset, ir_type_size[type])) {
1258 | ldr Rx(reg), [Rx(base_reg), #offset]
1261 | ldr Rw(reg), [Rx(base_reg), #offset]
1265 | ldrsh Rw(reg), [Rx(base_reg), #offset]
1267 | ldrh Rw(reg), [Rx(base_reg), #offset]
1272 | ldrsb Rw(reg), [Rx(base_reg), #offset]
1274 | ldrb Rw(reg), [Rx(base_reg), #offset]
1282 ir_emit_load_imm_int(ctx, IR_ADDR, index_reg, offset);
1285 IR_ASSERT(offset == 0);
1342 int32_t offset = IR_MEM_OFFSET(mem);
1345 if (aarch64_may_encode_addr_offset(offset, ir_type_size[type])) {
1347 | ldr Rd(reg-IR_REG_FP_FIRST), [Rx(base_reg), #offset]
1350 | ldr Rs(reg-IR_REG_FP_FIRST), [Rx(base_reg), #offset]
1355 ir_emit_load_imm_int(ctx, IR_ADDR, index_reg, offset);
1359 IR_ASSERT(offset == 0);
1384 int32_t offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[src].op3);
1387 if (aarch64_may_encode_imm12(offset)) {
1388 | add Rx(reg), Rx(base), #offset
1390 ir_emit_load_imm_int(ctx, IR_ADDR, IR_REG_INT_TMP, offset);
1432 int32_t offset = IR_MEM_OFFSET(mem);
1435 if (aarch64_may_encode_addr_offset(offset, ir_type_size[type])) {
1440 | str Rx(reg), [Rx(base_reg), #offset]
1443 | str Rw(reg), [Rx(base_reg), #offset]
1446 | strh Rw(reg), [Rx(base_reg), #offset]
1449 | strb Rw(reg), [Rx(base_reg), #offset]
1456 ir_emit_load_imm_int(ctx, IR_ADDR, index_reg, offset);
1459 IR_ASSERT(offset == 0);
1486 int32_t offset = IR_MEM_OFFSET(mem);
1489 if (aarch64_may_encode_addr_offset(offset, ir_type_size[type])) {
1491 | str Rd(reg-IR_REG_FP_FIRST), [Rx(base_reg), #offset]
1494 | str Rs(reg-IR_REG_FP_FIRST), [Rx(base_reg), #offset]
1499 ir_emit_load_imm_int(ctx, IR_ADDR, index_reg, offset);
1503 IR_ASSERT(offset == 0);
1574 int offset;
1577 offset = -(ctx->stack_frame_size+16);
1578 if (aarch64_may_encode_imm7_addr_offset(offset, 8)) {
1579 | stp x29, x30, [sp, #offset]!
1603 offset = ctx->stack_frame_size + sizeof(void*) * 2;
1606 offset = ctx->stack_frame_size + ctx->call_stack_size;
1613 offset -= sizeof(void*) * 2;
1614 if (aarch64_may_encode_imm7_addr_offset(offset, 8)) {
1615 | stp Rx(prev), Rx(i), [Rx(fp), #offset]
1617 IR_ASSERT(aarch64_may_encode_addr_offset(offset, 8));
1618 | str Rx(prev), [Rx(fp), #offset]
1619 | str Rx(i), [Rx(fp), #(offset+8)]
1624 offset -= sizeof(void*);
1625 | str Rx(prev), [Rx(fp), #offset]
1626 offset -= sizeof(void*);
1627 | str Rd(i-IR_REG_FP_FIRST), [Rx(fp), #offset]
1629 offset -= sizeof(void*) * 2;
1630 if (aarch64_may_encode_imm7_addr_offset(offset, 8)) {
1631 | stp Rd(prev-IR_REG_FP_FIRST), Rd(i-IR_REG_FP_FIRST), [Rx(fp), #offset]
1633 IR_ASSERT(aarch64_may_encode_addr_offset(offset, 8));
1634 | str Rd(prev-IR_REG_FP_FIRST), [Rx(fp), #offset]
1635 | str Rd(i-IR_REG_FP_FIRST), [Rx(fp), #(offset+8)]
1644 offset -= sizeof(void*);
1645 | str Rx(prev), [Rx(fp), #offset]
1647 offset -= sizeof(void*);
1648 | str Rd(prev-IR_REG_FP_FIRST), [Rx(fp), #offset]
1657 int offset;
1663 offset = ctx->locals_area_size + sizeof(void*) * 2;
1666 offset = ctx->locals_area_size + ctx->call_stack_size;
1673 offset += sizeof(void*) * ctx->gp_reg_params;
1676 if (aarch64_may_encode_imm7_addr_offset(offset, 8)) {
1677 | stp Rx(prev), Rx(int_reg_params[i]), [Rx(fp), #offset]
1679 IR_ASSERT(aarch64_may_encode_addr_offset(offset, 8));
1680 | str Rx(prev), [Rx(fp), #offset]
1681 | str Rx(int_reg_params[i]), [Rx(fp), #(offset+8)]
1684 offset += sizeof(void*) * 2;
1690 | str Rx(prev), [Rx(fp), #offset]
1691 offset += sizeof(void*);
1696 offset += 16 * ctx->fp_reg_params;
1699 | str Rd(fp_reg_params[i]-IR_REG_FP_FIRST), [Rx(fp), #offset]
1700 offset += 16;
1713 int offset;
1720 offset = ctx->stack_frame_size + sizeof(void*) * 2;
1722 offset = ctx->stack_frame_size + ctx->call_stack_size;
1729 offset -= sizeof(void*) * 2;
1730 if (aarch64_may_encode_imm7_addr_offset(offset, 8)) {
1731 | ldp Rx(prev), Rx(i), [Rx(fp), #offset]
1733 IR_ASSERT(aarch64_may_encode_addr_offset(offset, 8));
1734 | ldr Rx(prev), [Rx(fp), #offset]
1735 | ldr Rx(i), [Rx(fp), #(offset+8)]
1740 offset -= sizeof(void*);
1741 | ldr Rx(prev), [Rx(fp), #offset]
1742 offset -= sizeof(void*);
1743 | ldr Rd(i-IR_REG_FP_FIRST), [Rx(fp), #offset]
1745 offset -= sizeof(void*) * 2;
1746 if (aarch64_may_encode_imm7_addr_offset(offset, 8)) {
1747 | ldp Rd(prev-IR_REG_FP_FIRST), Rd(i-IR_REG_FP_FIRST), [Rx(fp), #offset]
1749 IR_ASSERT(aarch64_may_encode_addr_offset(offset, 8));
1750 | ldr Rd(prev-IR_REG_FP_FIRST), [Rx(fp), #offset]
1751 | ldr Rd(i-IR_REG_FP_FIRST), [Rx(fp), #(offset+8)]
1760 offset -= sizeof(void*);
1761 | ldr Rx(prev), [Rx(fp), #offset]
1763 offset -= sizeof(void*);
1764 | ldr Rd(prev-IR_REG_FP_FIRST), [Rx(fp), #offset]
2181 int64_t offset = ctx->ir_base[insn->op2].val.u64 - 1;
2195 ir_emit_load_imm_int(ctx, type, op2_reg, offset);
2203 | add Rx(def_reg), Rx(op1_reg), #offset
2212 | add Rw(def_reg), Rw(op1_reg), #offset
3298 int32_t offset = ir_ref_spill_slot_offset(ctx, insn->op1, &fp);
3302 | ldrsb Rw(def_reg), [Rx(fp), #offset]
3304 | ldrsb Rw(def_reg), [Rx(fp), #offset]
3307 | ldrsb Rx(def_reg), [Rx(fp), #offset]
3311 | ldrsh Rw(def_reg), [Rx(fp), #offset]
3314 | ldrsh Rx(def_reg), [Rx(fp), #offset]
3319 | ldrsw Rx(def_reg), [Rx(fp), #offset]
3357 int32_t offset = ir_ref_spill_slot_offset(ctx, insn->op1, &fp);
3360 | ldrb Rw(def_reg), [Rx(fp), #offset]
3362 | ldrh Rw(def_reg), [Rx(fp), #offset]
3366 | ldr Rw(def_reg), [Rx(fp), #offset]
3463 int32_t offset = ir_ref_spill_slot_offset(ctx, insn->op1, &fp);
3466 | ldr Rx(def_reg), [Rx(fp), #offset]
3469 | ldr Rw(def_reg), [Rx(fp), #offset]
3489 int32_t offset = ir_ref_spill_slot_offset(ctx, insn->op1, &fp);
3492 | ldr Rd(def_reg), [Rx(fp), #offset]
3495 | ldr Rs(def_reg), [Rx(fp), #offset]
3714 int32_t offset;
3718 offset = ir_var_spill_slot(ctx, insn->op1, &fp);
3719 | add Rx(def_reg), Rx(fp), #offset
3731 int32_t offset;
3736 offset = IR_SPILL_POS_TO_OFFSET(var_insn->op3);
3737 mem = IR_MEM_BO(fp, offset);
3755 int32_t offset;
3760 offset = IR_SPILL_POS_TO_OFFSET(var_insn->op3);
3772 mem = IR_MEM_BO(fp, offset);
3780 int32_t offset;
3787 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[addr_insn->op1].op3);
3788 offset += ctx->ir_base[addr_insn->op2].val.i32;
3789 return IR_MEM_BO(reg, offset);
3805 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[ref].op3);
3806 return IR_MEM_BO(reg, offset);
4178 int32_t offset;
4186 offset = 0;
4190 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
4201 | str Rx(tmp_reg), [Rx(op2_reg), #offset]
4210 int32_t offset;
4218 offset = 0;
4222 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
4237 | str Rx(tmp_reg), [Rx(op2_reg), #(offset+offsetof(ir_va_list, stack))]
4244 | str Rx(tmp_reg), [Rx(op2_reg), #(offset+offsetof(ir_va_list, gr_top))]
4247 | str Rw(tmp_reg), [Rx(op2_reg), #(offset+offsetof(ir_va_list, gr_offset))]
4250 | str wzr, [Rx(op2_reg), #(offset+offsetof(ir_va_list, gr_offset))]
4258 | str Rx(tmp_reg), [Rx(op2_reg), #(offset+offsetof(ir_va_list, vr_top))]
4261 | str Rw(tmp_reg), [Rx(op2_reg), #(offset+offsetof(ir_va_list, vr_offset))]
4264 | str wzr, [Rx(op2_reg), #(offset+offsetof(ir_va_list, vr_offset))]
4355 int32_t offset;
4363 offset = 0;
4367 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
4369 | ldr Rx(tmp_reg), [Rx(op2_reg), #offset]
4372 | str Rx(tmp_reg), [Rx(op2_reg), #offset]
4383 int32_t offset;
4391 offset = 0;
4395 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
4398 | ldr Rw(tmp_reg), [Rx(op2_reg), #(offset+offsetof(ir_va_list, gr_offset))]
4401 | ldr Rx(IR_REG_INT_TMP), [Rx(op2_reg), #(offset+offsetof(ir_va_list, gr_top))]
4406 | str Rw(tmp_reg), [Rx(op2_reg), #(offset+offsetof(ir_va_list, gr_offset))]
4409 | ldr Rx(tmp_reg), [Rx(op2_reg), #(offset+offsetof(ir_va_list, stack))]
4412 | str Rx(tmp_reg), [Rx(op2_reg), #(offset+offsetof(ir_va_list, stack))]
4415 | ldr Rw(tmp_reg), [Rx(op2_reg), #(offset+offsetof(ir_va_list, vr_offset))]
4418 | ldr Rx(IR_REG_INT_TMP), [Rx(op2_reg), #(offset+offsetof(ir_va_list, vr_top))]
4423 | str Rw(tmp_reg), [Rx(op2_reg), #(offset+offsetof(ir_va_list, vr_offset))]
4426 | ldr Rx(tmp_reg), [Rx(op2_reg), #(offset+offsetof(ir_va_list, stack))]
4429 | str Rx(tmp_reg), [Rx(op2_reg), #(offset+offsetof(ir_va_list, stack))]
5320 …it_param_move(ir_ctx *ctx, uint8_t type, ir_reg from_reg, ir_reg to_reg, ir_ref to, int32_t offset)
5334 ir_emit_load_mem_int(ctx, type, to_reg, IR_MEM_BO(fp, offset));
5344 ir_emit_load_mem_fp(ctx, type, to_reg, IR_MEM_BO(fp, offset));
6286 uint32_t offset = dasm_getpclabel(&data.dasm_state, data.jmp_table_label);
6287 ctx->jmp_table_offset = offset;
6292 uint32_t offset = dasm_getpclabel(&data.dasm_state, data.rodata_label);
6293 ctx->rodata_offset = offset;
6303 …uint32_t offset = dasm_getpclabel(&data.dasm_state, ctx->cfg_blocks_count + ctx->consts_count + 4 …
6304 insn->op3 = offset;
6389 … ir_add_veneer(dasm_State *Dst, void *buffer, uint32_t ins, int *b, uint32_t *cp, ptrdiff_t offset)
6477 na = (ptrdiff_t)cp + offset - (ptrdiff_t)veneer - 4;
