Lines Matching refs:insn
340 const ir_insn *insn;
348 insn = &ctx->ir_base[ref];
350 if (IR_IS_CONST_REF(insn->op1)) {
351 constraints->tmp_regs[n] = IR_TMP_REG(1, insn->type, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
353 } else if (ir_rule(ctx, insn->op1) == IR_STATIC_ALLOCA) {
357 if (IR_IS_CONST_REF(insn->op2) && insn->op1 != insn->op2) {
358 const ir_insn *val_insn = &ctx->ir_base[insn->op2];
359 switch (insn->op) {
365 constraints->tmp_regs[n] = IR_TMP_REG(2, insn->type, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
370 constraints->tmp_regs[n] = IR_TMP_REG(2, insn->type, IR_LOAD_SUB_REF, IR_SAVE_SUB_REF);
376 …ST(val_insn->op) || !aarch64_may_encode_logical_imm(val_insn->val.u64, ir_type_size[insn->type])) {
377 constraints->tmp_regs[n] = IR_TMP_REG(2, insn->type, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
384 constraints->tmp_regs[n] = IR_TMP_REG(2, insn->type, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
388 } else if (ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA) {
392 if (insn->op == IR_MOD) {
393 constraints->tmp_regs[n] = IR_TMP_REG(3, insn->type, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
395 …} else if (insn->op == IR_MUL_OV && (ir_type_size[insn->type] == 8 || IR_IS_TYPE_SIGNED(insn->type…
396 constraints->tmp_regs[n] = IR_TMP_REG(3, insn->type, IR_LOAD_SUB_REF, IR_SAVE_SUB_REF);
410 insn = &ctx->ir_base[ref];
412 if (IR_IS_CONST_REF(insn->op1)) {
413 constraints->tmp_regs[n] = IR_TMP_REG(1, insn->type, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
417 && (insn->op == IR_ROL || insn->op == IR_ROR)
418 && ir_type_size[insn->type] < 4) {
419 constraints->tmp_regs[n] = IR_TMP_REG(3, insn->type, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
422 && (insn->op == IR_ROL || insn->op == IR_ROR)
423 && ir_type_size[insn->type] < 4) {
424 if (insn->op == IR_ROL) {
427 constraints->tmp_regs[n] = IR_TMP_REG(3, insn->type, IR_LOAD_SUB_REF, IR_SAVE_SUB_REF);
429 } else if (rule == IR_SHIFT && insn->op == IR_ROL) {
430 constraints->tmp_regs[n] = IR_TMP_REG(3, insn->type, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
436 insn = &ctx->ir_base[ref];
438 if (IR_IS_CONST_REF(insn->op1)) {
439 constraints->tmp_regs[n] = IR_TMP_REG(1, insn->type, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
442 if (IR_IS_CONST_REF(insn->op2)) {
443 int64_t offset = ctx->ir_base[insn->op2].val.u64 - 1;
445 constraints->tmp_regs[n] = IR_TMP_REG(2, insn->type, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
452 insn = &ctx->ir_base[ref];
454 if (IR_IS_CONST_REF(insn->op1)) {
455 constraints->tmp_regs[n] = IR_TMP_REG(1, insn->type, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
458 constraints->tmp_regs[n] = IR_TMP_REG(3, insn->type, IR_USE_SUB_REF, IR_SAVE_SUB_REF);
463 insn = &ctx->ir_base[ref];
469 insn = &ctx->ir_base[ref];
471 if (IR_IS_CONST_REF(insn->op1)) {
472 constraints->tmp_regs[n] = IR_TMP_REG(1, insn->type, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
475 if (IR_IS_CONST_REF(insn->op2) && insn->op1 != insn->op2) {
476 constraints->tmp_regs[n] = IR_TMP_REG(2, insn->type, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
481 insn = &ctx->ir_base[ref];
483 if (IR_IS_CONST_REF(insn->op1)) {
484 constraints->tmp_regs[n] = IR_TMP_REG(1, insn->type, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
486 } else if (ir_rule(ctx, insn->op1) == IR_STATIC_ALLOCA) {
490 if (IR_IS_CONST_REF(insn->op2) && insn->op1 != insn->op2) {
491 insn = &ctx->ir_base[insn->op2];
492 if (IR_IS_SYM_CONST(insn->op) || !aarch64_may_encode_imm12(insn->val.u64)) {
493 constraints->tmp_regs[n] = IR_TMP_REG(2, insn->type, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
496 } else if (ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA) {
502 insn = &ctx->ir_base[ref];
504 if (IR_IS_CONST_REF(insn->op1)) {
505 const ir_insn *val_insn = &ctx->ir_base[insn->op1];
509 if (IR_IS_CONST_REF(insn->op2) && insn->op1 != insn->op2) {
510 const ir_insn *val_insn = &ctx->ir_base[insn->op2];
516 insn = &ctx->ir_base[ref];
517 if (IR_IS_CONST_REF(insn->op3)) {
518 insn = &ctx->ir_base[insn->op3];
519 constraints->tmp_regs[0] = IR_TMP_REG(3, insn->type, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
521 } else if (ir_rule(ctx, insn->op3) == IR_STATIC_ALLOCA) {
527 insn = &ctx->ir_base[ref];
529 if (IR_IS_CONST_REF(insn->op2)) {
530 IR_ASSERT(ctx->ir_base[insn->op2].type == IR_ADDR);
537 insn = &ctx->ir_base[ref];
539 if (IR_IS_CONST_REF(insn->op2)) {
540 IR_ASSERT(ctx->ir_base[insn->op2].type == IR_ADDR);
544 if (IR_IS_CONST_REF(insn->op3)) {
545 insn = &ctx->ir_base[insn->op3];
546 if (!IR_IS_TYPE_INT(insn->type) || IR_IS_SYM_CONST(insn->op) || insn->val.i64 != 0) {
547 constraints->tmp_regs[n] = IR_TMP_REG(3, insn->type, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
550 } else if (ir_rule(ctx, insn->op3) == IR_STATIC_ALLOCA) {
556 insn = &ctx->ir_base[ref];
558 if (IR_IS_CONST_REF(insn->op2)) {
559 insn = &ctx->ir_base[insn->op2];
560 constraints->tmp_regs[n] = IR_TMP_REG(2, insn->type, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
563 insn = &ctx->ir_base[insn->op2];
564 constraints->tmp_regs[n] = IR_TMP_REG(1, insn->type, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
571 insn = &ctx->ir_base[ref];
572 constraints->def_reg = (IR_IS_TYPE_INT(insn->type)) ? IR_REG_INT_RET1 : IR_REG_FP_RET1;
577 insn = &ctx->ir_base[ref];
578 if (insn->inputs_count > 2) {
580 constraints->hints_count = ir_get_args_regs(ctx, insn, constraints->hints);
581 if (!IR_IS_CONST_REF(insn->op2)) {
589 insn = &ctx->ir_base[ref];
591 if (IR_IS_CONST_REF(insn->op1)) {
592 …constraints->tmp_regs[n] = IR_TMP_REG(1, ctx->ir_base[insn->op1].type, IR_LOAD_SUB_REF, IR_DEF_SUB…
595 if (IR_IS_CONST_REF(insn->op2) || ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA) {
596 constraints->tmp_regs[n] = IR_TMP_REG(2, insn->type, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
599 if (IR_IS_CONST_REF(insn->op3) || ir_rule(ctx, insn->op3) == IR_STATIC_ALLOCA) {
600 constraints->tmp_regs[n] = IR_TMP_REG(3, insn->type, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
686 ir_insn *insn = &ctx->ir_base[*p];
687 if (insn->op != IR_LOAD && (insn->op != IR_STORE || insn->op3 == addr_ref)) {
701 ir_insn *insn = &ctx->ir_base[ref];
703 switch (insn->op) {
714 if (IR_IS_TYPE_INT(ctx->ir_base[insn->op1].type)) {
722 if (IR_IS_TYPE_INT(insn->type)) {
723 if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
724 op2_insn = &ctx->ir_base[insn->op2];
727 } else if (IR_IS_CONST_REF(insn->op1)) {
741 if (IR_IS_TYPE_INT(insn->type)) {
742 if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
743 op2_insn = &ctx->ir_base[insn->op2];
746 } else if (IR_IS_CONST_REF(insn->op1)) {
763 IR_ASSERT(IR_IS_TYPE_INT(insn->type));
766 IR_ASSERT(IR_IS_TYPE_INT(insn->type));
769 if (IR_IS_TYPE_INT(insn->type)) {
770 if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
771 op2_insn = &ctx->ir_base[insn->op2];
774 } else if (IR_IS_CONST_REF(insn->op1)) {
779 if (IR_IS_TYPE_UNSIGNED(insn->type)) {
792 if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
793 op2_insn = &ctx->ir_base[insn->op2];
796 } else if (IR_IS_CONST_REF(insn->op1)) {
799 if (IR_IS_TYPE_UNSIGNED(insn->type)) {
811 IR_ASSERT(IR_IS_TYPE_INT(insn->type));
815 if (IR_IS_TYPE_INT(insn->type)) {
821 if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
822 op2_insn = &ctx->ir_base[insn->op2];
825 } else if (IR_IS_CONST_REF(insn->op1)) {
835 if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
836 op2_insn = &ctx->ir_base[insn->op2];
839 } else if (IR_IS_CONST_REF(insn->op1)) {
849 if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
850 op2_insn = &ctx->ir_base[insn->op2];
853 } else if (IR_IS_CONST_REF(insn->op1)) {
859 if (IR_IS_CONST_REF(insn->op2)) {
861 op2_insn = &ctx->ir_base[insn->op2];
864 } else if (IR_IS_CONST_REF(insn->op1)) {
868 } else if (ir_type_size[insn->type] >= 4) {
885 if (IR_IS_CONST_REF(insn->op2)) {
887 op2_insn = &ctx->ir_base[insn->op2];
890 } else if (IR_IS_CONST_REF(insn->op1)) {
901 if (IR_IS_TYPE_INT(insn->type)) {
909 if (IR_IS_TYPE_INT(insn->type)) {
917 return insn->op | IR_MAY_REUSE;
919 if (IR_IS_TYPE_INT(insn->type) && IR_IS_TYPE_INT(ctx->ir_base[insn->op1].type)) {
920 return insn->op | IR_MAY_REUSE;
922 return insn->op;
936 if (IR_IS_CONST_REF(insn->op2) && ctx->cfg_map[ref] == 1) {
937 ir_insn *val = &ctx->ir_base[insn->op2];
948 ir_match_fuse_addr(ctx, insn->op2, insn->type);
949 if (IR_IS_TYPE_INT(insn->type)) {
956 ir_match_fuse_addr(ctx, insn->op2, ctx->ir_base[insn->op3].type);
957 if (IR_IS_TYPE_INT(ctx->ir_base[insn->op3].type)) {
964 if (IR_REGSET_IN(IR_REGSET_UNION((ir_regset)ctx->fixed_regset, IR_REGSET_FIXED), insn->op2)) {
969 if (IR_IS_TYPE_INT(ctx->ir_base[insn->op2].type)) {
970 …if ((ctx->flags & IR_OPT_CODEGEN) && ir_in_same_block(ctx, insn->op2) && ctx->use_lists[insn->op2]…
971 ir_insn *op_insn = &ctx->ir_base[insn->op2];
973 if (!ctx->rules[insn->op2]) {
974 ctx->rules[insn->op2] = ir_match_insn(ctx, insn->op2);
976 if (ctx->rules[insn->op2] == IR_BINOP_INT) {
978 && ctx->ir_base[op_insn->op1].op2 == insn->op3) {
979 ctx->rules[insn->op2] = IR_FUSED | IR_BINOP_INT;
984 && ctx->ir_base[op_insn->op2].op2 == insn->op3) {
986 ctx->rules[insn->op2] = IR_FUSED | IR_BINOP_INT;
1003 return IR_SKIPPED | insn->op;
1005 if (!insn->op2) {
1007 } else if (IR_IS_TYPE_INT(ctx->ir_base[insn->op2].type)) {
1013 if (!IR_IS_CONST_REF(insn->op2) && ctx->use_lists[insn->op2].count == 1) {
1014 op2_insn = &ctx->ir_base[insn->op2];
1017 ctx->rules[insn->op2] = IR_FUSED | IR_CMP_INT;
1020 ctx->rules[insn->op2] = IR_FUSED | IR_CMP_FP;
1023 } else if (op2_insn->op == IR_OVERFLOW && ir_in_same_block(ctx, insn->op2)) {
1024 ctx->rules[insn->op2] = IR_FUSED | IR_SIMPLE | IR_OVERFLOW;
1028 if (IR_IS_TYPE_INT(ctx->ir_base[insn->op2].type)) {
1036 if (!IR_IS_CONST_REF(insn->op2) && ctx->use_lists[insn->op2].count == 1) {
1037 op2_insn = &ctx->ir_base[insn->op2];
1040 && (insn->op2 == ref - 1 ||
1041 (insn->op2 == ctx->prev_ref[ref] - 1
1044 ctx->rules[insn->op2] = IR_FUSED | IR_CMP_INT;
1047 ctx->rules[insn->op2] = IR_FUSED | IR_CMP_FP;
1050 } else if (op2_insn->op == IR_OVERFLOW && ir_in_same_block(ctx, insn->op2)) {
1051 ctx->rules[insn->op2] = IR_FUSED | IR_SIMPLE | IR_OVERFLOW;
1055 return insn->op;
1058 if ((ctx->ir_base[insn->op2].op == IR_ALLOCA) || (ctx->ir_base[insn->op2].op == IR_VADDR)) {
1059 ir_use_list *use_list = &ctx->use_lists[insn->op2];
1065 if (use_insn->op3 == insn->op2) {
1069 if (use_insn->op2 == insn->op2) {
1102 return insn->op;
1318 ir_insn *insn = &ctx->ir_base[src];
1321 if (type == IR_FLOAT && insn->val.u32 == 0) {
1323 } else if (type == IR_DOUBLE && insn->val.u64 == 0) {
1400 ir_insn *insn = &ctx->ir_base[src];
1402 if (insn->op == IR_SYM || insn->op == IR_FUNC) {
1403 void *addr = ir_sym_val(ctx, insn);
1406 } else if (insn->op == IR_STR) {
1413 ir_emit_load_imm_int(ctx, type, reg, insn->val.i64);
1788 static void ir_emit_binop_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
1792 ir_type type = insn->type;
1793 ir_ref op1 = insn->op1;
1794 ir_ref op2 = insn->op2;
1813 switch (insn->op) {
1891 switch (insn->op) {
1937 static void ir_emit_min_max_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
1941 ir_type type = insn->type;
1942 ir_ref op1 = insn->op1;
1943 ir_ref op2 = insn->op2;
1965 if (insn->op == IR_MIN) {
1972 IR_ASSERT(insn->op == IR_MAX);
1981 if (insn->op == IR_MIN) {
1988 IR_ASSERT(insn->op == IR_MAX);
2002 static void ir_emit_overflow(ir_ctx *ctx, ir_ref def, ir_insn *insn)
2007 ir_insn *math_insn = &ctx->ir_base[insn->op1];
2020 ir_emit_store(ctx, insn->type, def, def_reg);
2024 static void ir_emit_overflow_and_branch(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_…
2028 ir_insn *overflow_insn = &ctx->ir_base[insn->op2];
2067 static void ir_emit_reg_binop_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
2071 ir_insn *op_insn = &ctx->ir_base[insn->op2];
2074 ir_reg op2_reg = ctx->regs[insn->op2][2];
2077 IR_ASSERT(insn->op == IR_RSTORE);
2078 reg = insn->op3;
2134 static void ir_emit_mul_div_mod_pwr2(ir_ctx *ctx, ir_ref def, ir_insn *insn)
2138 ir_type type = insn->type;
2139 ir_ref op1 = insn->op1;
2143 IR_ASSERT(IR_IS_CONST_REF(insn->op2));
2144 IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[insn->op2].op));
2151 if (insn->op == IR_MUL) {
2152 uint32_t shift = IR_LOG2(ctx->ir_base[insn->op2].val.u64);
2158 } else if (insn->op == IR_DIV) {
2159 uint32_t shift = IR_LOG2(ctx->ir_base[insn->op2].val.u64);
2162 IR_ASSERT(insn->op == IR_MOD);
2163 uint64_t mask = ctx->ir_base[insn->op2].val.u64 - 1;
2171 static void ir_emit_sdiv_pwr2(ir_ctx *ctx, ir_ref def, ir_insn *insn)
2175 ir_type type = insn->type;
2176 ir_ref op1 = insn->op1;
2180 uint32_t shift = IR_LOG2(ctx->ir_base[insn->op2].val.u64);
2181 int64_t offset = ctx->ir_base[insn->op2].val.u64 - 1;
2184 IR_ASSERT(IR_IS_CONST_REF(insn->op2));
2185 IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[insn->op2].op));
2229 static void ir_emit_smod_pwr2(ir_ctx *ctx, ir_ref def, ir_insn *insn)
2233 ir_type type = insn->type;
2234 ir_ref op1 = insn->op1;
2238 // uint32_t shift = IR_LOG2(ctx->ir_base[insn->op2].val.u64);
2239 uint64_t mask = ctx->ir_base[insn->op2].val.u64 - 1;
2242 IR_ASSERT(IR_IS_CONST_REF(insn->op2));
2243 IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[insn->op2].op));
2274 static void ir_emit_shift(ir_ctx *ctx, ir_ref def, ir_insn *insn)
2278 ir_type type = insn->type;
2287 ir_emit_load(ctx, type, op1_reg, insn->op1);
2291 ir_emit_load(ctx, type, op2_reg, insn->op2);
2293 switch (insn->op) {
2379 static void ir_emit_shift_const(ir_ctx *ctx, ir_ref def, ir_insn *insn)
2383 uint32_t shift = ctx->ir_base[insn->op2].val.u64;
2384 ir_type type = insn->type;
2385 ir_ref op1 = insn->op1;
2390 IR_ASSERT(IR_IS_CONST_REF(insn->op2));
2391 IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[insn->op2].op));
2398 switch (insn->op) {
2464 static void ir_emit_op_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
2468 ir_type type = insn->type;
2469 ir_ref op1 = insn->op1;
2479 if (insn->op == IR_NOT) {
2480 if (insn->type == IR_BOOL) {
2484 | ASM_REG_REG_OP mvn, insn->type, def_reg, op1_reg
2486 } else if (insn->op == IR_NEG) {
2487 | ASM_REG_REG_OP neg, insn->type, def_reg, op1_reg
2488 } else if (insn->op == IR_ABS) {
2496 } else if (insn->op == IR_CTLZ) {
2508 } else if (insn->op == IR_CTTZ) {
2509 | ASM_REG_REG_OP rbit, insn->type, def_reg, op1_reg
2510 | ASM_REG_REG_OP clz, insn->type, def_reg, def_reg
2512 IR_ASSERT(insn->op == IR_BSWAP);
2513 | ASM_REG_REG_OP rev, insn->type, def_reg, op1_reg
2520 static void ir_emit_ctpop(ir_ctx *ctx, ir_ref def, ir_insn *insn)
2524 ir_type type = insn->type;
2525 ir_ref op1 = insn->op1;
2538 switch (ir_type_size[insn->type]) {
2573 static void ir_emit_op_fp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
2577 ir_type type = insn->type;
2578 ir_ref op1 = insn->op1;
2588 if (insn->op == IR_NEG) {
2596 IR_ASSERT(insn->op == IR_ABS);
2605 ir_emit_store(ctx, insn->type, def, def_reg);
2609 static void ir_emit_binop_fp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
2613 ir_type type = insn->type;
2614 ir_ref op1 = insn->op1;
2615 ir_ref op2 = insn->op2;
2631 switch (insn->op) {
2654 ir_emit_store(ctx, insn->type, def, def_reg);
2721 static void ir_emit_cmp_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
2725 ir_type type = ctx->ir_base[insn->op1].type;
2726 ir_op op = insn->op;
2727 ir_ref op1 = insn->op1;
2728 ir_ref op2 = insn->op2;
2746 if (IR_IS_CONST_REF(insn->op2)
2747 && !IR_IS_SYM_CONST(ctx->ir_base[insn->op2].op)
2748 && ctx->ir_base[insn->op2].val.u64 == 0) {
2753 ir_emit_store(ctx, insn->type, def, def_reg);
2760 ir_emit_store(ctx, insn->type, def, def_reg);
2805 ir_emit_store(ctx, insn->type, def, def_reg);
2852 static void ir_emit_cmp_fp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
2856 ir_op op = ir_emit_cmp_fp_common(ctx, def, insn);
2896 ir_emit_store(ctx, insn->type, def, def_reg);
2959 static void ir_emit_jcc(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_t next_block, ui…
3059 static void ir_emit_cmp_and_branch_int(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_t…
3061 ir_insn *cmp_insn = &ctx->ir_base[insn->op2];
3066 ir_reg op1_reg = ctx->regs[insn->op2][1];
3067 ir_reg op2_reg = ctx->regs[insn->op2][2];
3103 ir_emit_jcc(ctx, b, def, insn, next_block, op, 1);
3106 static void ir_emit_cmp_and_branch_fp(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_t …
3108 ir_op op = ir_emit_cmp_fp_common(ctx, insn->op2, &ctx->ir_base[insn->op2]);
3109 ir_emit_jcc(ctx, b, def, insn, next_block, op, 0);
3112 static void ir_emit_if_int(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn, uint32_t next_block)
3114 ir_type type = ctx->ir_base[insn->op2].type;
3119 if (IR_IS_CONST_REF(insn->op2)) {
3123 if (ir_const_is_true(&ctx->ir_base[insn->op2])) {
3133 } else if (ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA) {
3145 ir_emit_load(ctx, type, op2_reg, insn->op2);
3148 ir_emit_jcc(ctx, b, def, insn, next_block, IR_NE, 1);
3151 static void ir_emit_cond(ir_ctx *ctx, ir_ref def, ir_insn *insn)
3155 ir_type type = insn->type;
3156 ir_ref op1 = insn->op1;
3157 ir_ref op2 = insn->op2;
3158 ir_ref op3 = insn->op3;
3223 static void ir_emit_return_int(ir_ctx *ctx, ir_ref ref, ir_insn *insn)
3228 ir_type type = ctx->ir_base[insn->op2].type;
3233 ir_emit_load(ctx, type, IR_REG_INT_RET1, insn->op2);
3239 static void ir_emit_return_fp(ir_ctx *ctx, ir_ref ref, ir_insn *insn)
3242 ir_type type = ctx->ir_base[insn->op2].type;
3248 ir_emit_load(ctx, type, IR_REG_FP_RET1, insn->op2);
3254 static void ir_emit_sext(ir_ctx *ctx, ir_ref def, ir_insn *insn)
3256 ir_type dst_type = insn->type;
3257 ir_type src_type = ctx->ir_base[insn->op1].type;
3269 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
3294 } else if (IR_IS_CONST_REF(insn->op1)) {
3298 int32_t offset = ir_ref_spill_slot_offset(ctx, insn->op1, &fp);
3327 static void ir_emit_zext(ir_ctx *ctx, ir_ref def, ir_insn *insn)
3329 ir_type dst_type = insn->type;
3330 ir_type src_type = ctx->ir_base[insn->op1].type;
3342 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
3353 } else if (IR_IS_CONST_REF(insn->op1)) {
3357 int32_t offset = ir_ref_spill_slot_offset(ctx, insn->op1, &fp);
3374 static void ir_emit_trunc(ir_ctx *ctx, ir_ref def, ir_insn *insn)
3378 ir_type dst_type = insn->type;
3379 ir_type src_type = ctx->ir_base[insn->op1].type;
3389 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
3400 ir_emit_load(ctx, dst_type, def_reg, insn->op1);
3407 static void ir_emit_bitcast(ir_ctx *ctx, ir_ref def, ir_insn *insn)
3409 ir_type dst_type = insn->type;
3410 ir_type src_type = ctx->ir_base[insn->op1].type;
3420 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
3426 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
3432 ir_emit_load(ctx, dst_type, def_reg, insn->op1);
3438 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
3444 ir_emit_load(ctx, dst_type, def_reg, insn->op1);
3451 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
3459 } else if (IR_IS_CONST_REF(insn->op1)) {
3463 int32_t offset = ir_ref_spill_slot_offset(ctx, insn->op1, &fp);
3477 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
3485 } else if (IR_IS_CONST_REF(insn->op1)) {
3489 int32_t offset = ir_ref_spill_slot_offset(ctx, insn->op1, &fp);
3504 static void ir_emit_int2fp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
3506 ir_type dst_type = insn->type;
3507 ir_type src_type = ctx->ir_base[insn->op1].type;
3518 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
3569 static void ir_emit_fp2int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
3571 ir_type dst_type = insn->type;
3572 ir_type src_type = ctx->ir_base[insn->op1].type;
3583 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
3623 static void ir_emit_fp2fp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
3625 ir_type dst_type = insn->type;
3626 ir_type src_type = ctx->ir_base[insn->op1].type;
3637 ir_emit_load(ctx, src_type, op1_reg, insn->op1);
3654 static void ir_emit_copy_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
3656 ir_ref type = insn->type;
3663 ir_emit_load(ctx, type, op1_reg, insn->op1);
3670 ir_emit_load(ctx, type, def_reg, insn->op1);
3681 static void ir_emit_copy_fp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
3683 ir_type type = insn->type;
3690 ir_emit_load(ctx, type, op1_reg, insn->op1);
3697 ir_emit_load(ctx, type, def_reg, insn->op1);
3708 static void ir_emit_vaddr(ir_ctx *ctx, ir_ref def, ir_insn *insn)
3712 ir_ref type = insn->type;
3718 offset = ir_var_spill_slot(ctx, insn->op1, &fp);
3725 static void ir_emit_vload(ir_ctx *ctx, ir_ref def, ir_insn *insn)
3727 ir_insn *var_insn = &ctx->ir_base[insn->op2];
3728 ir_ref type = insn->type;
3748 static void ir_emit_vstore(ir_ctx *ctx, ir_ref ref, ir_insn *insn)
3750 ir_insn *var_insn = &ctx->ir_base[insn->op2];
3751 ir_insn *val_insn = &ctx->ir_base[insn->op3];
3763 && !IR_IS_CONST_REF(insn->op3)
3764 && ir_rule(ctx, insn->op3) != IR_STATIC_ALLOCA
3765 && ir_is_same_mem_var(ctx, insn->op3, var_insn->op3)) {
3770 ir_emit_load(ctx, type, op3_reg, insn->op3);
3810 static void ir_emit_load_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
3812 ir_ref type = insn->type;
3825 IR_ASSERT(ctx->ir_base[insn->op2].type == IR_ADDR);
3826 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
3829 } else if (IR_IS_CONST_REF(insn->op2)) {
3831 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
3834 IR_ASSERT(ir_rule(ctx, insn->op2) & IR_FUSED);
3835 mem = ir_fuse_addr(ctx, def, insn->op2);
3850 static void ir_emit_load_fp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
3852 ir_ref type = insn->type;
3865 IR_ASSERT(ctx->ir_base[insn->op2].type == IR_ADDR);
3866 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
3869 } else if (IR_IS_CONST_REF(insn->op2)) {
3871 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
3874 IR_ASSERT(ir_rule(ctx, insn->op2) & IR_FUSED);
3875 mem = ir_fuse_addr(ctx, def, insn->op2);
3890 static void ir_emit_store_int(ir_ctx *ctx, ir_ref ref, ir_insn *insn)
3892 ir_insn *val_insn = &ctx->ir_base[insn->op3];
3901 IR_ASSERT(ctx->ir_base[insn->op2].type == IR_ADDR);
3902 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
3906 IR_ASSERT(!IR_IS_CONST_REF(insn->op2) && (ir_rule(ctx, insn->op2) & IR_FUSED));
3907 mem = ir_fuse_addr(ctx, ref, insn->op2);
3908 if (!IR_IS_CONST_REF(insn->op3)
3910 && ir_rule(ctx, insn->op3) != IR_STATIC_ALLOCA
3911 && ir_is_same_spill_slot(ctx, insn->op3, mem)) {
3912 if (!ir_may_avoid_spill_load(ctx, insn->op3, ref)) {
3914 ir_emit_load(ctx, type, op3_reg, insn->op3);
3924 ir_emit_load(ctx, type, op3_reg, insn->op3);
3927 …IR_ASSERT(IR_IS_CONST_REF(insn->op3) && !IR_IS_SYM_CONST(ctx->ir_base[insn->op3].op) && ctx->ir_ba…
3933 static void ir_emit_store_fp(ir_ctx *ctx, ir_ref ref, ir_insn *insn)
3935 ir_ref type = ctx->ir_base[insn->op3].type;
3944 IR_ASSERT(ctx->ir_base[insn->op2].type == IR_ADDR);
3945 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
3949 IR_ASSERT(!IR_IS_CONST_REF(insn->op2) && (ir_rule(ctx, insn->op2) & IR_FUSED));
3950 mem = ir_fuse_addr(ctx, ref, insn->op2);
3951 if (!IR_IS_CONST_REF(insn->op3)
3953 && ir_rule(ctx, insn->op3) != IR_STATIC_ALLOCA
3954 && ir_is_same_spill_slot(ctx, insn->op3, mem)) {
3955 if (!ir_may_avoid_spill_load(ctx, insn->op3, ref)) {
3957 ir_emit_load(ctx, type, op3_reg, insn->op3);
3966 ir_emit_load(ctx, type, op3_reg, insn->op3);
3971 static void ir_emit_rload(ir_ctx *ctx, ir_ref def, ir_insn *insn)
3973 ir_reg src_reg = insn->op2;
3974 ir_type type = insn->type;
3989 if (!insn->op3 || !ir_is_same_spill_slot(ctx, def, IR_MEM_BO(ctx->spill_base, insn->op3))) {
4002 && (!insn->op3 || !ir_is_same_spill_slot(ctx, def, IR_MEM_BO(ctx->spill_base, insn->op3)))) {
4009 static void ir_emit_rstore(ir_ctx *ctx, ir_ref ref, ir_insn *insn)
4011 ir_ref type = ctx->ir_base[insn->op2].type;
4013 ir_reg dst_reg = insn->op3;
4018 ir_emit_load(ctx, type, op2_reg, insn->op2);
4029 ir_emit_load(ctx, type, dst_reg, insn->op2);
4033 static void ir_emit_alloca(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4043 if (IR_IS_CONST_REF(insn->op2)) {
4044 ir_insn *val = &ctx->ir_base[insn->op2];
4065 ir_type type = ctx->ir_base[insn->op2].type;
4072 ir_emit_load(ctx, type, op2_reg, insn->op2);
4081 ir_emit_store(ctx, insn->type, def, def_reg);
4088 static void ir_emit_afree(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4093 if (IR_IS_CONST_REF(insn->op2)) {
4094 ir_insn *val = &ctx->ir_base[insn->op2];
4110 ir_type type = ctx->ir_base[insn->op2].type;
4116 ir_emit_load(ctx, type, op2_reg, insn->op2);
4125 static void ir_emit_block_begin(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4138 static void ir_emit_block_end(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4147 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
4169 static void ir_emit_va_start(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4184 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
4188 IR_ASSERT(ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA);
4190 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
4216 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
4220 IR_ASSERT(ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA);
4222 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
4269 static void ir_emit_va_copy(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4283 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
4287 IR_ASSERT(ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA);
4289 op2_offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
4294 ir_emit_load(ctx, IR_ADDR, op3_reg, insn->op3);
4298 IR_ASSERT(ir_rule(ctx, insn->op3) == IR_STATIC_ALLOCA);
4300 op3_offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op3].op3);
4316 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
4320 IR_ASSERT(ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA);
4322 op2_offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
4327 ir_emit_load(ctx, IR_ADDR, op3_reg, insn->op3);
4331 IR_ASSERT(ir_rule(ctx, insn->op3) == IR_STATIC_ALLOCA);
4333 op3_offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op3].op3);
4346 static void ir_emit_va_arg(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4351 ir_type type = insn->type;
4361 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
4365 IR_ASSERT(ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA);
4367 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
4379 ir_type type = insn->type;
4389 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
4393 IR_ASSERT(ir_rule(ctx, insn->op2) == IR_STATIC_ALLOCA);
4395 offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[insn->op2].op3);
4438 static void ir_emit_switch(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn)
4452 type = ctx->ir_base[insn->op2].type;
4492 ir_emit_load(ctx, type, op2_reg, insn->op2);
4560 ir_insn *insn = &ctx->ir_base[bb->end];
4562 if (insn->op == IR_IJMP && IR_IS_CONST_REF(insn->op2)) {
4568 void *addr = ir_jmp_addr(ctx, insn, &ctx->ir_base[insn->op2]);
4609 static int32_t ir_call_used_stack(ir_ctx *ctx, ir_insn *insn)
4619 const ir_proto_t *proto = ir_call_proto(ctx, insn);
4620 …int last_named_input = (proto && (proto->flags & IR_VARARG_FUNC)) ? proto->params_count + 2 : insn…
4623 n = insn->inputs_count;
4625 type = ctx->ir_base[ir_insn_op(insn, j)].type;
4648 static int32_t ir_emit_arguments(ir_ctx *ctx, ir_ref def, ir_insn *insn, ir_reg tmp_reg)
4670 n = insn->inputs_count;
4679 if (insn->op == IR_CALL && (ctx->flags & IR_PREALLOCATED_STACK)) {
4683 used_stack = ir_call_used_stack(ctx, insn);
4691 if (insn->op == IR_TAILCALL && !(ctx->flags & IR_USE_FRAME_POINTER)) {
4702 const ir_proto_t *proto = ir_call_proto(ctx, insn);
4703 …int last_named_input = (proto && (proto->flags & IR_VARARG_FUNC)) ? proto->params_count + 2 : insn…
4710 arg = ir_insn_op(insn, j);
4776 arg = ir_insn_op(insn, j);
4842 static void ir_emit_call_ex(ir_ctx *ctx, ir_ref def, ir_insn *insn, int32_t used_stack)
4848 if (IR_IS_CONST_REF(insn->op2)) {
4849 void *addr = ir_call_addr(ctx, insn, &ctx->ir_base[insn->op2]);
4863 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
4873 if (insn->type != IR_VOID) {
4874 if (IR_IS_TYPE_INT(insn->type)) {
4878 ir_emit_mov(ctx, insn->type, def_reg, IR_REG_INT_RET1);
4881 ir_emit_store(ctx, insn->type, def, def_reg);
4884 ir_emit_store(ctx, insn->type, def, IR_REG_INT_RET1);
4887 IR_ASSERT(IR_IS_TYPE_FP(insn->type));
4891 ir_emit_fp_mov(ctx, insn->type, def_reg, IR_REG_FP_RET1);
4894 ir_emit_store(ctx, insn->type, def, def_reg);
4897 ir_emit_store(ctx, insn->type, def, IR_REG_FP_RET1);
4903 static void ir_emit_call(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4905 int32_t used_stack = ir_emit_arguments(ctx, def, insn, ctx->regs[def][1]);
4906 ir_emit_call_ex(ctx, def, insn, used_stack);
4909 static void ir_emit_tailcall(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4913 int32_t used_stack = ir_emit_arguments(ctx, def, insn, ctx->regs[def][1]);
4916 ir_emit_call_ex(ctx, def, insn, used_stack);
4923 if (IR_IS_CONST_REF(insn->op2)) {
4924 void *addr = ir_call_addr(ctx, insn, &ctx->ir_base[insn->op2]);
4938 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
4944 static void ir_emit_ijmp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4953 ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
4956 } else if (IR_IS_CONST_REF(insn->op2)) {
4957 void *addr = ir_jmp_addr(ctx, insn, &ctx->ir_base[insn->op2]);
4970 static void ir_emit_guard(ir_ctx *ctx, ir_ref def, ir_insn *insn)
4975 ir_type type = ctx->ir_base[insn->op2].type;
4978 if (IR_IS_CONST_REF(insn->op2)) {
4979 bool is_true = ir_ref_is_true(ctx, insn->op2);
4981 if ((insn->op == IR_GUARD && !is_true) || (insn->op == IR_GUARD_NOT && is_true)) {
4982 if (IR_IS_CONST_REF(insn->op3)) {
4983 void *addr = ir_jmp_addr(ctx, insn, &ctx->ir_base[insn->op3]);
5001 ir_emit_load(ctx, type, op2_reg, insn->op2);
5004 if (IR_IS_CONST_REF(insn->op3)) {
5005 void *addr = ir_jmp_addr(ctx, insn, &ctx->ir_base[insn->op3]);
5007 if (insn->op == IR_GUARD) {
5116 static void ir_emit_guard_cmp_int(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn)
5120 ir_insn *cmp_insn = &ctx->ir_base[insn->op2];
5125 ir_reg op1_reg = ctx->regs[insn->op2][1];
5126 ir_reg op2_reg = ctx->regs[insn->op2][2];
5140 addr = ir_jmp_addr(ctx, insn, &ctx->ir_base[insn->op3]);
5163 if (insn->op == IR_GUARD_NOT) {
5172 if (insn->op == IR_GUARD) {
5179 static void ir_emit_guard_cmp_fp(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *insn)
5181 ir_op op = ir_emit_cmp_fp_common(ctx, insn->op2, &ctx->ir_base[insn->op2]);
5182 void *addr = ir_jmp_addr(ctx, insn, &ctx->ir_base[insn->op3]);
5184 if (insn->op == IR_GUARD) {
5190 static void ir_emit_guard_overflow(ir_ctx *ctx, ir_ref def, ir_insn *insn)
5194 ir_insn *overflow_insn = &ctx->ir_base[insn->op2];
5197 void *addr = ir_jmp_addr(ctx, insn, &ctx->ir_base[insn->op3]);
5201 if (insn->op == IR_GUARD) {
5207 if (insn->op == IR_GUARD) {
5213 if (insn->op == IR_GUARD) {
5221 static void ir_emit_tls(ir_ctx *ctx, ir_ref def, ir_insn *insn)
5237 |//??? MEM_ACCESS_64_WITH_UOFFSET_64 ldr, Rx(reg), Rx(reg), #insn->op2, TMP1
5238 |//??? MEM_ACCESS_64_WITH_UOFFSET_64 ldr, Rx(reg), Rx(reg), #insn->op3, TMP1
5243 || if (insn->op3 == IR_NULL) {
5244 | ldr Rx(reg), [Rx(reg), #insn->op2]
5247 | ldr Rx(reg), [Rx(reg), #insn->op2]
5248 | ldr Rx(reg), [Rx(reg), #insn->op3]
5251 ||//??? IR_ASSERT(insn->op2 <= LDR_STR_PIMM64);
5252 | ldr Rx(reg), [Rx(reg), #insn->op2]
5260 static void ir_emit_exitcall(ir_ctx *ctx, ir_ref def, ir_insn *insn)
5307 if (IR_IS_CONST_REF(insn->op2)) {
5308 void *addr = ir_call_addr(ctx, insn, &ctx->ir_base[insn->op2]);
5323 ir_emit_mov(ctx, insn->type, def_reg, IR_REG_INT_RET1);
5326 ir_emit_store(ctx, insn->type, def, def_reg);
5362 ir_insn *insn;
5383 insn = &ctx->ir_base[use];
5384 if (insn->op == IR_PARAM) {
5385 if (IR_IS_TYPE_INT(insn->type)) {
5408 ir_emit_param_move(ctx, insn->type, src_reg, dst_reg, use, stack_offset);
5411 ir_emit_store(ctx, insn->type, use, dst_reg);
5418 stack_offset += IR_MAX(sizeof(void*), ir_type_size[insn->type]);
5471 ir_insn *insn;
5493 insn = &ctx->ir_base[use];
5494 if (insn->op == IR_PARAM) {
5495 if (IR_IS_TYPE_INT(insn->type)) {
5523 stack_offset += IR_MAX(sizeof(void*), ir_type_size[insn->type]);
5524 param_stack_size += IR_MAX(sizeof(void*), ir_type_size[insn->type]);
5539 ir_insn *insn;
5560 for (i = bb->start, insn = ctx->ir_base + i, rule = ctx->rules + i; i <= bb->end;) {
5561 switch (ctx->rules ? *rule : insn->op) {
5588 if (insn->op == IR_VLOAD
5592 } else if (insn->op != IR_PARAM) {
5593 reg = ir_get_free_reg(insn->type, available);
5602 ival->type = insn->type;
5606 if (insn->op == IR_PARAM && reg == IR_REG_NONE) {
5611 } else if (insn->op == IR_PARAM) {
5615 } else if (insn->op == IR_VAR) {
5620 … int32_t stack_spill_pos = insn->op3 = ir_allocate_spill_slot(ctx, insn->type, &data->ra_data);
5633 ival->type = insn->type;
5645 ival->type = insn->type;
5655 insn_flags = ir_op_flags[insn->op];
5662 ir_ref *ops = insn->ops;
5677 n = insn->inputs_count;
5678 for (j = 1, p = insn->ops + 1; j <= n; j++, p++) {
5691 } else if (j > 1 && input == insn->op1 && ctx->regs[i][1] != IR_REG_NONE) {
5703 n = ir_insn_len(insn);
5705 insn += n;
5723 ir_insn *insn;
5725 for (i = 1, insn = ctx->ir_base + 1; i < ctx->insns_count;) {
5726 if (insn->op == IR_CALL) {
5727 call_stack_size = ir_call_used_stack(ctx, insn);
5732 n = ir_insn_len(insn);
5734 insn += n;
5825 ir_insn *insn;
5905 insn = ctx->ir_base + i;
5907 uint32_t label = ctx->cfg_blocks_count + ctx->consts_count + 4 + insn->op3;
5911 ctx->entries[insn->op3] = i;
5915 n = ir_insn_len(insn);
5917 insn += n;
5933 ir_emit_mul_div_mod_pwr2(ctx, i, insn);
5936 ir_emit_sdiv_pwr2(ctx, i, insn);
5939 ir_emit_smod_pwr2(ctx, i, insn);
5942 ir_emit_shift(ctx, i, insn);
5945 ir_emit_shift_const(ctx, i, insn);
5948 ir_emit_ctpop(ctx, i, insn);
5951 ir_emit_op_int(ctx, i, insn);
5954 ir_emit_op_fp(ctx, i, insn);
5957 ir_emit_binop_int(ctx, i, insn);
5960 ir_emit_binop_fp(ctx, i, insn);
5963 ir_emit_cmp_int(ctx, i, insn);
5966 ir_emit_cmp_fp(ctx, i, insn);
5969 ir_emit_sext(ctx, i, insn);
5972 ir_emit_zext(ctx, i, insn);
5975 ir_emit_trunc(ctx, i, insn);
5979 ir_emit_bitcast(ctx, i, insn);
5982 ir_emit_int2fp(ctx, i, insn);
5985 ir_emit_fp2int(ctx, i, insn);
5988 ir_emit_fp2fp(ctx, i, insn);
5991 ir_emit_copy_int(ctx, i, insn);
5994 ir_emit_copy_fp(ctx, i, insn);
5997 ir_emit_cmp_and_branch_int(ctx, b, i, insn, _ir_next_block(ctx, _b));
6000 ir_emit_cmp_and_branch_fp(ctx, b, i, insn, _ir_next_block(ctx, _b));
6003 ir_emit_guard_cmp_int(ctx, b, i, insn);
6006 ir_emit_guard_cmp_fp(ctx, b, i, insn);
6009 ir_emit_if_int(ctx, b, i, insn, _ir_next_block(ctx, _b));
6012 ir_emit_cond(ctx, i, insn);
6015 ir_emit_switch(ctx, b, i, insn);
6018 ir_emit_min_max_int(ctx, i, insn);
6021 ir_emit_overflow(ctx, i, insn);
6024 ir_emit_overflow_and_branch(ctx, b, i, insn, _ir_next_block(ctx, _b));
6056 ir_emit_return_int(ctx, i, insn);
6059 ir_emit_return_fp(ctx, i, insn);
6062 ir_emit_call(ctx, i, insn);
6065 ir_emit_tailcall(ctx, i, insn);
6068 ir_emit_ijmp(ctx, i, insn);
6071 ir_emit_reg_binop_int(ctx, i, insn);
6074 ir_emit_vaddr(ctx, i, insn);
6077 ir_emit_vload(ctx, i, insn);
6080 ir_emit_vstore(ctx, i, insn);
6083 ir_emit_rload(ctx, i, insn);
6086 ir_emit_rstore(ctx, i, insn);
6089 ir_emit_load_int(ctx, i, insn);
6092 ir_emit_load_fp(ctx, i, insn);
6095 ir_emit_store_int(ctx, i, insn);
6098 ir_emit_store_fp(ctx, i, insn);
6101 ir_emit_alloca(ctx, i, insn);
6104 ir_emit_va_start(ctx, i, insn);
6107 ir_emit_va_copy(ctx, i, insn);
6110 ir_emit_va_arg(ctx, i, insn);
6113 ir_emit_afree(ctx, i, insn);
6116 ir_emit_block_begin(ctx, i, insn);
6119 ir_emit_block_end(ctx, i, insn);
6125 ir_emit_exitcall(ctx, i, insn);
6129 ir_emit_guard(ctx, i, insn);
6132 ir_emit_guard_overflow(ctx, i, insn);
6135 ir_emit_tls(ctx, i, insn);
6148 n = ir_insn_len(insn);
6150 insn += n;
6174 insn = &ctx->ir_base[-i];
6175 if (IR_IS_TYPE_FP(insn->type)) {
6184 if (insn->type == IR_DOUBLE) {
6187 |.long insn->val.u32, insn->val.u32_hi
6189 IR_ASSERT(insn->type == IR_FLOAT);
6192 |.long insn->val.u32
6194 } else if (insn->op == IR_STR) {
6196 const char *str = ir_get_str(ctx, insn->val.str);
6312 ir_insn *insn = &ctx->ir_base[ctx->entries[--i]];
6313 …set = dasm_getpclabel(&data.dasm_state, ctx->cfg_blocks_count + ctx->consts_count + 4 + insn->op3);
6314 insn->op3 = offset;
