Lines Matching refs:ZEND_CPU_EDX_MASK
25 #define ZEND_CPU_EDX_MASK (1U<<31) macro
66 ZEND_CPU_FEATURE_FPU = (1<<0 | ZEND_CPU_EDX_MASK),
67 ZEND_CPU_FEATURE_VME = (1<<1 | ZEND_CPU_EDX_MASK),
68 ZEND_CPU_FEATURE_DE = (1<<2 | ZEND_CPU_EDX_MASK),
69 ZEND_CPU_FEATURE_PSE = (1<<3 | ZEND_CPU_EDX_MASK),
70 ZEND_CPU_FEATURE_TSC = (1<<4 | ZEND_CPU_EDX_MASK),
71 ZEND_CPU_FEATURE_MSR = (1<<5 | ZEND_CPU_EDX_MASK),
72 ZEND_CPU_FEATURE_PAE = (1<<6 | ZEND_CPU_EDX_MASK),
73 ZEND_CPU_FEATURE_MCE = (1<<7 | ZEND_CPU_EDX_MASK),
74 ZEND_CPU_FEATURE_CX8 = (1<<8 | ZEND_CPU_EDX_MASK),
75 ZEND_CPU_FEATURE_APIC = (1<<9 | ZEND_CPU_EDX_MASK),
77 ZEND_CPU_FEATURE_SEP = (1<<11 | ZEND_CPU_EDX_MASK),
78 ZEND_CPU_FEATURE_MTRR = (1<<12 | ZEND_CPU_EDX_MASK),
79 ZEND_CPU_FEATURE_PGE = (1<<13 | ZEND_CPU_EDX_MASK),
80 ZEND_CPU_FEATURE_MCA = (1<<14 | ZEND_CPU_EDX_MASK),
81 ZEND_CPU_FEATURE_CMOV = (1<<15 | ZEND_CPU_EDX_MASK),
82 ZEND_CPU_FEATURE_PAT = (1<<16 | ZEND_CPU_EDX_MASK),
83 ZEND_CPU_FEATURE_PSE36 = (1<<17 | ZEND_CPU_EDX_MASK),
84 ZEND_CPU_FEATURE_PN = (1<<18 | ZEND_CPU_EDX_MASK),
85 ZEND_CPU_FEATURE_CLFLUSH = (1<<19 | ZEND_CPU_EDX_MASK),
87 ZEND_CPU_FEATURE_DS = (1<<21 | ZEND_CPU_EDX_MASK),
88 ZEND_CPU_FEATURE_ACPI = (1<<22 | ZEND_CPU_EDX_MASK),
89 ZEND_CPU_FEATURE_MMX = (1<<23 | ZEND_CPU_EDX_MASK),
90 ZEND_CPU_FEATURE_FXSR = (1<<24 | ZEND_CPU_EDX_MASK),
91 ZEND_CPU_FEATURE_SSE = (1<<25 | ZEND_CPU_EDX_MASK),
92 ZEND_CPU_FEATURE_SSE2 = (1<<26 | ZEND_CPU_EDX_MASK),
93 ZEND_CPU_FEATURE_SS = (1<<27 | ZEND_CPU_EDX_MASK),
94 ZEND_CPU_FEATURE_HT = (1<<28 | ZEND_CPU_EDX_MASK),
95 ZEND_CPU_FEATURE_TM = (1<<29 | ZEND_CPU_EDX_MASK)
