Lines Matching refs:Z_ZV
478 | LOAD_ADDR reg, Z_ZV(addr)
488 | PUSH_ADDR Z_ZV(addr), tmp_reg
579 | MEM_OP2_2 sse_ins, xmm(reg-ZREG_XMM0), qword, Z_ZV(addr), tmp_reg
592 || if (IS_SIGNED_32BIT(Z_ZV(addr))) {
593 | SSE_AVX_INS sse_ins, avx_ins, xmm(reg-ZREG_XMM0), qword [Z_ZV(addr)]
595 | LOAD_ADDR r0, Z_ZV(addr)
599 | SSE_AVX_INS sse_ins, avx_ins, xmm(reg-ZREG_XMM0), qword [Z_ZV(addr)]
639 | SSE_GET_LONG reg, Z_LVAL_P(Z_ZV(addr)), tmp_reg
665 || if (IS_SIGNED_32BIT(Z_ZV(addr))) {
666 | SSE_AVX_INS movsd, vmovsd, xmm(reg-ZREG_XMM0), qword [Z_ZV(addr)]
668 | LOAD_ADDR r0, Z_ZV(addr)
672 | SSE_AVX_INS movsd, vmovsd, xmm(reg-ZREG_XMM0), qword [Z_ZV(addr)]
731 | MEM_OP3_3 avx_ins, xmm(reg-ZREG_XMM0), xmm(op1_reg-ZREG_XMM0), qword, Z_ZV(addr), tmp_reg
778 || if (!IS_SIGNED_32BIT(Z_LVAL_P(Z_ZV(addr)))) {
779 | mov64 tmp_reg, Z_LVAL_P(Z_ZV(addr))
782 | long_ins Ra(reg), Z_LVAL_P(Z_ZV(addr))
785 | long_ins Ra(reg), Z_LVAL_P(Z_ZV(addr))
836 || if (Z_LVAL_P(Z_ZV(addr)) == 0) {
840 || if (!IS_SIGNED_32BIT(Z_LVAL_P(Z_ZV(addr)))) {
841 | mov64 Ra(reg), Z_LVAL_P(Z_ZV(addr))
843 | mov Ra(reg), Z_LVAL_P(Z_ZV(addr))
846 | mov Ra(reg), Z_LVAL_P(Z_ZV(addr))
4361 Z_LVAL_P(Z_ZV(op2_addr)) == 2) {
4371 Z_LVAL_P(Z_ZV(op2_addr)) > 0 &&
4372 zend_long_is_power_of_two(Z_LVAL_P(Z_ZV(op2_addr)))) {
4374 | shl Ra(result_reg), zend_long_floor_log2(Z_LVAL_P(Z_ZV(op2_addr)))
4377 Z_LVAL_P(Z_ZV(op1_addr)) == 2) {
4387 Z_LVAL_P(Z_ZV(op1_addr)) > 0 &&
4388 zend_long_is_power_of_two(Z_LVAL_P(Z_ZV(op1_addr)))) {
4390 | shl Ra(result_reg), zend_long_floor_log2(Z_LVAL_P(Z_ZV(op1_addr)))
4393 zend_long_is_power_of_two(Z_LVAL_P(Z_ZV(op2_addr))))) {
4395 | shr Ra(result_reg), zend_long_floor_log2(Z_LVAL_P(Z_ZV(op2_addr)))
4400 IS_SIGNED_32BIT(Z_LVAL_P(Z_ZV(op2_addr)))) {
4401 | lea Ra(result_reg), [Ra(Z_REG(op1_addr))+Z_LVAL_P(Z_ZV(op2_addr))]
4406 IS_SIGNED_32BIT(Z_LVAL_P(Z_ZV(op1_addr)))) {
4407 | lea Ra(result_reg), [Ra(Z_REG(op2_addr))+Z_LVAL_P(Z_ZV(op1_addr))]
4412 IS_SIGNED_32BIT(-Z_LVAL_P(Z_ZV(op2_addr)))) {
4413 | lea Ra(result_reg), [Ra(Z_REG(op1_addr))-Z_LVAL_P(Z_ZV(op2_addr))]
4418 && Z_LVAL_P(Z_ZV(op2_addr)) == 0) {
4480 ((Z_MODE(op1_addr) == IS_CONST_ZVAL && Z_LVAL_P(Z_ZV(op1_addr)) == 1) ||
4481 (Z_MODE(op2_addr) == IS_CONST_ZVAL && Z_LVAL_P(Z_ZV(op2_addr)) == 1))) {
4642 && Z_LVAL_P(Z_ZV(op2_addr)) == 0) {
4652 && Z_LVAL_P(Z_ZV(op2_addr)) == 0) {
4709 Z_MODE(val_addr) == IS_CONST_ZVAL && Z_DVAL_P(Z_ZV(val_addr)) == 2.0) {
4730 Z_MODE(val_addr) == IS_CONST_ZVAL && Z_DVAL_P(Z_ZV(val_addr)) == 2.0) {
5071 zend_long op2_lval = Z_LVAL_P(Z_ZV(op2_addr));
5115 zend_long op2_lval = Z_LVAL_P(Z_ZV(op2_addr));
5154 zend_long op2_lval = Z_LVAL_P(Z_ZV(op2_addr));
5553 val = Z_LVAL_P(Z_ZV(op2_addr));
6026 zval *zv = Z_ZV(val_addr);
6360 zval *zv = Z_ZV(val_addr);
6613 | LOAD_ADDR FCARG2a, (Z_ZV(op2_addr) + 1)
6870 | LOAD_ADDR FCARG2a, (Z_ZV(op2_addr) + 1)
6992 ZEND_ASSERT(Z_TYPE_P(Z_ZV(op1_addr)) == IS_LONG);
6993 op1_min = op1_max = Z_LVAL_P(Z_ZV(op1_addr));
7002 ZEND_ASSERT(Z_TYPE_P(Z_ZV(op2_addr)) == IS_LONG);
7003 op2_min = op2_max = Z_LVAL_P(Z_ZV(op2_addr));
7108 if (Z_MODE(op2_addr) == IS_CONST_ZVAL && Z_LVAL_P(Z_ZV(op2_addr)) == 0) {
7114 if (Z_MODE(op1_addr) == IS_CONST_ZVAL && Z_LVAL_P(Z_ZV(op1_addr)) == 0) {
7121 | LONG_OP_WITH_CONST cmp, op2_addr, Z_LVAL_P(Z_ZV(op1_addr))
7124 | LONG_OP_WITH_CONST cmp, op1_addr, Z_LVAL_P(Z_ZV(op2_addr))
7127 if (Z_MODE(op2_addr) == IS_CONST_ZVAL && Z_LVAL_P(Z_ZV(op2_addr)) == 0) {
8324 if (zend_is_identical(Z_ZV(op1_addr), Z_ZV(op2_addr))) {
8349 } else if (Z_MODE(op1_addr) == IS_CONST_ZVAL && Z_TYPE_P(Z_ZV(op1_addr)) <= IS_TRUE) {
8350 zval *val = Z_ZV(op1_addr);
8397 } else if (Z_MODE(op2_addr) == IS_CONST_ZVAL && Z_TYPE_P(Z_ZV(op2_addr)) <= IS_TRUE) {
8398 zval *val = Z_ZV(op2_addr);
8538 if (zend_is_true(Z_ZV(op1_addr))) {
12183 | LOAD_ADDR FCARG2a, (Z_ZV(op2_addr) + 1)
12467 | LOAD_ADDR FCARG2a, (Z_ZV(op2_addr) + 1)
12591 | LOAD_ADDR FCARG2a, (Z_ZV(op2_addr) + 1)
