Lines Matching refs:Z_REG
480 | LOAD_BASE_ADDR reg, Z_REG(addr), Z_OFFSET(addr)
490 | PUSH_BASE_ADDR Z_REG(addr), Z_OFFSET(addr), tmp_reg
506 | mov reg, byte [Ra(Z_REG(addr))+Z_OFFSET(addr)+offsetof(zval,u1.v.type)]
511 | mov reg, dword [Ra(Z_REG(addr))+Z_OFFSET(addr)+offsetof(zval,u1.type_info)]
516 | mov dword [Ra(Z_REG(addr))+Z_OFFSET(addr)+offsetof(zval,u1.type_info)], type
537 | mov reg, aword [Ra(Z_REG(addr))+Z_OFFSET(addr)]
542 | mov aword [Ra(Z_REG(addr))+Z_OFFSET(addr)], val
547 | mov reg, dword [Ra(Z_REG(addr))+Z_OFFSET(addr)+4]
552 | mov dword [Ra(Z_REG(addr))+Z_OFFSET(addr)+4], val
581 | sse_ins xmm(reg-ZREG_XMM0), qword [Ra(Z_REG(addr))+Z_OFFSET(addr)]
583 | sse_ins xmm(reg-ZREG_XMM0), xmm(Z_REG(addr)-ZREG_XMM0)
602 | SSE_AVX_INS sse_ins, avx_ins, xmm(reg-ZREG_XMM0), qword [Ra(Z_REG(addr))+Z_OFFSET(addr)]
604 | SSE_AVX_INS sse_ins, avx_ins, xmm(reg-ZREG_XMM0), xmm(Z_REG(addr)-ZREG_XMM0)
643 | vcvtsi2sd xmm(reg-ZREG_XMM0), xmm(reg-ZREG_XMM0), aword [Ra(Z_REG(addr))+Z_OFFSET(addr)]
646 | cvtsi2sd xmm(reg-ZREG_XMM0), aword [Ra(Z_REG(addr))+Z_OFFSET(addr)]
651 | vcvtsi2sd xmm(reg-ZREG_XMM0), xmm(reg-ZREG_XMM0), Ra(Z_REG(addr))
654 | cvtsi2sd xmm(reg-ZREG_XMM0), Ra(Z_REG(addr))
662 || if (Z_MODE(addr) != IS_REG || reg != Z_REG(addr)) {
675 | SSE_AVX_INS movsd, vmovsd, xmm(reg-ZREG_XMM0), qword [Ra(Z_REG(addr))+Z_OFFSET(addr)]
677 | SSE_AVX_INS movaps, vmovaps, xmm(reg-ZREG_XMM0), xmm(Z_REG(addr)-ZREG_XMM0)
720 || if (reg != Z_REG(addr)) {
721 | SSE_AVX_INS movaps, vmovaps, xmm(Z_REG(addr)-ZREG_XMM0), xmm(reg-ZREG_XMM0)
725 | SSE_AVX_INS movsd, vmovsd, qword [Ra(Z_REG(addr))+Z_OFFSET(addr)], xmm(reg-ZREG_XMM0)
733 | avx_ins xmm(reg-ZREG_XMM0), xmm(op1_reg-ZREG_XMM0), qword [Ra(Z_REG(addr))+Z_OFFSET(addr)]
735 | avx_ins xmm(reg-ZREG_XMM0), xmm(op1_reg-ZREG_XMM0), xmm(Z_REG(addr)-ZREG_XMM0)
788 | long_ins Ra(reg), aword [Ra(Z_REG(addr))+Z_OFFSET(addr)]
790 | long_ins Ra(reg), Ra(Z_REG(addr))
798 | long_ins aword [Ra(Z_REG(op1_addr))+Z_OFFSET(op1_addr)], lval
800 | long_ins Ra(Z_REG(op1_addr)), lval
811 | long_ins aword [Ra(Z_REG(op1_addr))+Z_OFFSET(op1_addr)], r0
813 | long_ins aword [Ra(Z_REG(op1_addr))+Z_OFFSET(op1_addr)], lval
816 | long_ins aword [Ra(Z_REG(op1_addr))+Z_OFFSET(op1_addr)], lval
822 | long_ins Ra(Z_REG(op1_addr)), r0
824 | long_ins Ra(Z_REG(op1_addr)), lval
827 | long_ins Ra(Z_REG(op1_addr)), lval
850 | mov Ra(reg), aword [Ra(Z_REG(addr))+Z_OFFSET(addr)]
852 || if (reg != Z_REG(addr)) {
853 | mov Ra(reg), Ra(Z_REG(addr))
912 | mov Ra(Z_REG(addr)), lval
915 | mov aword [Ra(Z_REG(addr))+Z_OFFSET(addr)], lval
922 || zend_reg dst_reg = (Z_MODE(dst_addr) == IS_REG) ? Z_REG(dst_addr) : ZREG_XMM0;
939 || zend_reg dst_reg = (Z_MODE(dst_addr) == IS_REG) ? Z_REG(dst_addr) : ZREG_XMM0;
943 | xor Ra(Z_REG(dst_addr)), Ra(Z_REG(dst_addr))
948 | mov64 Ra(Z_REG(dst_addr)), ((uintptr_t)Z_LVAL_P(zv))
976 || Z_REG(dst_addr) : ((Z_MODE(res_addr) == IS_REG) ? Z_REG(res_addr) : ZREG_XMM0);
995 | SSE_GET_LONG Z_REG(dst_addr), Z_LVAL_P(zv), ZREG_R0
996 | SSE_SET_ZVAL_DVAL res_addr, Z_REG(dst_addr)
998 | SSE_GET_LONG Z_REG(res_addr), Z_LVAL_P(zv), ZREG_R0
999 | SSE_SET_ZVAL_DVAL dst_addr, Z_REG(res_addr)
1007 | xor Ra(Z_REG(dst_addr)), Ra(Z_REG(dst_addr))
1008 | SET_ZVAL_LVAL res_addr, Ra(Z_REG(dst_addr))
1010 | xor Ra(Z_REG(res_addr)), Ra(Z_REG(res_addr))
1011 | SET_ZVAL_LVAL dst_addr, Ra(Z_REG(res_addr))
1017 | mov64 Ra(Z_REG(dst_addr)), ((uintptr_t)Z_LVAL_P(zv))
1018 | SET_ZVAL_LVAL res_addr, Ra(Z_REG(dst_addr))
1020 | mov64 Ra(Z_REG(res_addr)), ((uintptr_t)Z_LVAL_P(zv))
1021 | SET_ZVAL_LVAL dst_addr, Ra(Z_REG(res_addr))
1029 | SET_ZVAL_LVAL res_addr, Ra(Z_REG(dst_addr))
1032 | SET_ZVAL_LVAL dst_addr, Ra(Z_REG(res_addr))
1040 | SET_ZVAL_LVAL res_addr, Ra(Z_REG(dst_addr))
1043 | SET_ZVAL_LVAL dst_addr, Ra(Z_REG(res_addr))
1091 || if (Z_MODE(dst_addr) != IS_REG || Z_REG(dst_addr) != Z_REG(src_addr)) {
1092 | SET_ZVAL_LVAL dst_addr, Ra(Z_REG(src_addr))
1095 | GET_ZVAL_LVAL Z_REG(dst_addr), src_addr
1102 | SSE_SET_ZVAL_DVAL dst_addr, Z_REG(src_addr)
1104 | SSE_GET_ZVAL_DVAL Z_REG(dst_addr), src_addr
1117 || if ((tmp_reg1 == tmp_reg2 || tmp_reg1 == Z_REG(src_addr))) {
1137 || if (Z_MODE(dst_addr) != IS_REG || Z_REG(dst_addr) != Z_REG(src_addr)) {
1138 | SET_ZVAL_LVAL dst_addr, Ra(Z_REG(src_addr))
1140 || if (Z_MODE(res_addr) != IS_REG || Z_REG(res_addr) != Z_REG(src_addr)) {
1141 | SET_ZVAL_LVAL res_addr, Ra(Z_REG(src_addr))
1144 | GET_ZVAL_LVAL Z_REG(dst_addr), src_addr
1145 || if (Z_MODE(res_addr) != IS_REG || Z_REG(res_addr) != Z_REG(dst_addr)) {
1146 | SET_ZVAL_LVAL res_addr, Ra(Z_REG(dst_addr))
1149 | GET_ZVAL_LVAL Z_REG(res_addr), src_addr
1150 | SET_ZVAL_LVAL dst_addr, Ra(Z_REG(res_addr))
1158 | SSE_SET_ZVAL_DVAL dst_addr, Z_REG(src_addr)
1159 | SSE_SET_ZVAL_DVAL res_addr, Z_REG(src_addr)
1161 | SSE_GET_ZVAL_DVAL Z_REG(dst_addr), src_addr
1162 | SSE_SET_ZVAL_DVAL res_addr, Z_REG(dst_addr)
1164 | SSE_GET_ZVAL_DVAL Z_REG(res_addr), src_addr
1165 | SSE_SET_ZVAL_DVAL dst_addr, Z_REG(res_addr)
1181 || if (tmp_reg1 == tmp_reg2 || tmp_reg1 == Z_REG(src_addr)) {
1242 | cmp byte [Ra(Z_REG(addr))+Z_OFFSET(addr)+offsetof(zval, u1.v.type)], val
1247 | IF_TYPE byte [Ra(Z_REG(addr))+Z_OFFSET(addr)+offsetof(zval, u1.v.type)], val, label
1252 | IF_NOT_TYPE byte [Ra(Z_REG(addr))+Z_OFFSET(addr)+offsetof(zval, u1.v.type)], val, label
1277 | IF_FLAGS byte [Ra(Z_REG(addr))+Z_OFFSET(addr)+offsetof(zval, u1.v.type_flags)], mask, label
1282 | IF_NOT_FLAGS byte [Ra(Z_REG(addr))+Z_OFFSET(addr)+offsetof(zval, u1.v.type_flags)], mask, label
1469 || if (Z_REG(addr) != ZREG_FP) {
1475 || if (Z_REG(addr) != ZREG_FCARG1a || Z_OFFSET(addr) != 0) {
3838 | SET_ZVAL_LVAL dst, Ra(Z_REG(src))
3843 | SSE_SET_ZVAL_DVAL dst, Z_REG(src)
3859 | GET_ZVAL_LVAL Z_REG(dst), src
3861 | SSE_GET_ZVAL_DVAL Z_REG(dst), src
3933 | mov Ra(Z_REG(dst)), Ra(Z_REG(src))
3935 | SSE_AVX_INS movaps, vmovaps, xmm(Z_REG(dst)-ZREG_XMM0), xmm(Z_REG(src)-ZREG_XMM0)
4269 tmp_reg = Z_REG(op1_def_addr);
4271 tmp_reg = Z_REG(op1_addr);
4344 && zend_jit_opline_uses_reg(opline, Z_REG(res_addr))) {
4347 result_reg = Z_REG(res_addr);
4350 result_reg = Z_REG(op1_addr);
4351 } else if (Z_REG(res_addr) != ZREG_R0) {
4363 | lea Ra(result_reg), [Ra(Z_REG(op1_addr))+Ra(Z_REG(op1_addr))]
4379 | lea Ra(result_reg), [Ra(Z_REG(op2_addr))+Ra(Z_REG(op2_addr))]
4401 | lea Ra(result_reg), [Ra(Z_REG(op1_addr))+Z_LVAL_P(Z_ZV(op2_addr))]
4407 | lea Ra(result_reg), [Ra(Z_REG(op2_addr))+Z_LVAL_P(Z_ZV(op1_addr))]
4413 | lea Ra(result_reg), [Ra(Z_REG(op1_addr))-Z_LVAL_P(Z_ZV(op2_addr))]
4426 if (Z_MODE(res_addr) == IS_MEM_ZVAL && Z_REG(res_addr) == ZREG_R0) {
4443 if (Z_MODE(res_addr) == IS_REG && result_reg != Z_REG(res_addr)) {
4444 | mov Ra(Z_REG(res_addr)), Ra(result_reg)
4462 …if (Z_MODE(op1_addr) != IS_MEM_ZVAL || Z_REG(op1_addr) != Z_REG(res_addr) || Z_OFFSET(op1_addr) !=…
4486 | movd xmm(Z_REG(res_addr)-ZREG_XMM0), Ra(tmp_reg)
4499 | movd xmm(Z_REG(res_addr)-ZREG_XMM0), Ra(tmp_reg)
4543 (Z_MODE(res_addr) == IS_REG) ? Z_REG(res_addr) : ZREG_XMM0;
4546 if (Z_MODE(res_addr) == IS_MEM_ZVAL && Z_REG(res_addr) == ZREG_R0) {
4555 if (Z_MODE(res_addr) == IS_MEM_ZVAL && Z_REG(res_addr) == ZREG_R0) {
4589 if (Z_MODE(res_addr) == IS_MEM_ZVAL && Z_REG(res_addr) == ZREG_R0) {
4597 …&& (Z_MODE(res_addr) != IS_REG || Z_MODE(op1_addr) != IS_REG || Z_REG(res_addr) != Z_REG(op1_addr)…
4599 result_reg = Z_REG(res_addr);
4604 if (Z_MODE(res_addr) == IS_MEM_ZVAL && Z_REG(res_addr) == ZREG_R0) {
4622 result_reg = Z_REG(res_addr);
4625 result_reg = Z_REG(op1_addr);
4635 op1_reg = Z_REG(op1_addr);
4663 …if (Z_MODE(op1_addr) != IS_MEM_ZVAL || Z_REG(op1_addr) != Z_REG(res_addr) || Z_OFFSET(op1_addr) !=…
4684 result_reg = Z_REG(res_addr);
4686 result_reg = Z_REG(op1_addr);
4688 result_reg = Z_REG(op2_addr);
4698 op1_reg = Z_REG(op1_addr);
4701 op1_reg = Z_REG(op2_addr);
4711 } else if (Z_MODE(res_addr) == IS_MEM_ZVAL && Z_REG(res_addr) == ZREG_R0) {
4732 } else if (Z_MODE(res_addr) == IS_MEM_ZVAL && Z_REG(res_addr) == ZREG_R0) {
4742 …if (Z_MODE(op1_addr) != IS_MEM_ZVAL || Z_REG(op1_addr) != Z_REG(res_addr) || Z_OFFSET(op1_addr) !=…
4917 } else if (Z_REG(res_addr) != ZREG_FCARG1a || Z_OFFSET(res_addr) != 0) {
4962 } else if (Z_MODE(res_addr) == IS_MEM_ZVAL && Z_REG(res_addr) == ZREG_RX) {
5052 result_reg = Z_REG(res_addr);
5055 result_reg = Z_REG(op1_addr);
5056 } else if (Z_REG(res_addr) != ZREG_R0) {
5083 | lea Ra(result_reg), [Ra(Z_REG(op1_addr))+Ra(Z_REG(op1_addr))]
5089 if (Z_MODE(op2_addr) != IS_REG || Z_REG(op2_addr) != ZREG_RCX) {
5130 if (Z_MODE(op2_addr) != IS_REG || Z_REG(op2_addr) != ZREG_RCX) {
5169 if (Z_MODE(res_addr) == IS_MEM_ZVAL && Z_REG(res_addr) == ZREG_R0) {
5180 if (Z_MODE(res_addr) == IS_MEM_ZVAL && Z_REG(res_addr) == ZREG_RAX) {
5182 } else if (Z_MODE(res_addr) == IS_MEM_ZVAL && Z_REG(res_addr) == ZREG_RCX) {
5198 if (Z_MODE(res_addr) == IS_MEM_ZVAL && Z_REG(res_addr) == ZREG_RAX) {
5200 } else if (Z_MODE(res_addr) == IS_MEM_ZVAL && Z_REG(res_addr) == ZREG_RCX) {
5207 | cmp aword [Ra(Z_REG(op2_addr))+Z_OFFSET(op2_addr)], 0
5209 | test Ra(Z_REG(op2_addr)), Ra(Z_REG(op2_addr))
5224 | cmp aword [Ra(Z_REG(op2_addr))+Z_OFFSET(op2_addr)], -1
5226 | cmp Ra(Z_REG(op2_addr)), -1
5233 …if (Z_MODE(op1_addr) != IS_MEM_ZVAL || Z_REG(op1_addr) != Z_REG(res_addr) || Z_OFFSET(op1_addr) !=…
5243 if (Z_MODE(res_addr) == IS_MEM_ZVAL && Z_REG(res_addr) == ZREG_RAX) {
5254 | idiv aword [Ra(Z_REG(op2_addr))+Z_OFFSET(op2_addr)]
5256 | idiv Ra(Z_REG(op2_addr))
5258 if (Z_MODE(res_addr) == IS_MEM_ZVAL && Z_REG(res_addr) == ZREG_RAX) {
5268 if (Z_MODE(res_addr) == IS_MEM_ZVAL && Z_REG(res_addr) == ZREG_R0) {
5280 if (Z_MODE(res_addr) != IS_REG || Z_REG(res_addr) != result_reg) {
5284 …if (Z_MODE(op1_addr) != IS_MEM_ZVAL || Z_REG(op1_addr) != Z_REG(res_addr) || Z_OFFSET(op1_addr) !=…
5301 } else if (Z_REG(res_addr) != ZREG_FCARG1a || Z_OFFSET(res_addr) != 0) {
5354 } else if (Z_MODE(res_addr) == IS_MEM_ZVAL && Z_REG(res_addr) == ZREG_RX) {
5415 …if (Z_MODE(op1_addr) == IS_MEM_ZVAL && Z_REG(op1_addr) == Z_REG(res_addr) && Z_OFFSET(op1_addr) ==…
5416 if (Z_REG(res_addr) != ZREG_FCARG1a || Z_OFFSET(res_addr) != 0) {
5424 if (Z_REG(res_addr) != ZREG_FCARG1a || Z_OFFSET(res_addr) != 0) {
5453 if (Z_REG(res_addr) != ZREG_FCARG1a || Z_OFFSET(res_addr) != 0) {
5474 if (Z_MODE(res_addr) == IS_MEM_ZVAL && Z_REG(res_addr) == ZREG_RX) {
6018 if (Z_MODE(var_addr) == IS_REG || Z_REG(var_addr) != ZREG_R0) {
6060 ZEND_ASSERT(Z_MODE(val_addr) == IS_MEM_ZVAL && Z_REG(val_addr) == ZREG_FP);
6077 ZEND_ASSERT(Z_REG(var_addr) != ZREG_R2);
6078 if (Z_MODE(val_addr) != IS_MEM_ZVAL || Z_REG(val_addr) != ZREG_R2 || Z_OFFSET(val_addr) != 0) {
6179 …if (Z_MODE(val_addr) != IS_MEM_ZVAL || Z_REG(val_addr) != ZREG_FCARG2a || Z_OFFSET(val_addr) != 0)…
6241 ZEND_ASSERT(Z_REG(val_addr) == ZREG_FP);
6242 if (Z_REG(var_addr) != ZREG_FP) {
6243 | mov aword T1, Ra(Z_REG(var_addr)) // save
6248 if (Z_REG(var_addr) != ZREG_FP) {
6249 | mov Ra(Z_REG(var_addr)), aword T1 // restore
6251 …if (Z_MODE(var_addr) != IS_MEM_ZVAL || Z_REG(var_addr) != ZREG_FCARG1a || Z_OFFSET(var_addr) != 0)…
6260 …if (Z_MODE(var_addr) != IS_MEM_ZVAL || Z_REG(var_addr) != ZREG_FCARG1a || Z_OFFSET(var_addr) != 0)…
6263 …if (Z_MODE(val_addr) != IS_MEM_ZVAL || Z_REG(val_addr) != ZREG_FCARG2a || Z_OFFSET(val_addr) != 0)…
6313 if (Z_MODE(var_addr) == IS_REG || Z_REG(var_use_addr) != ZREG_R0) {
6323 …if (Z_MODE(var_use_addr) != IS_MEM_ZVAL || Z_REG(var_use_addr) != ref_reg || Z_OFFSET(var_use_addr…
6347 if (Z_REG(var_use_addr) == ZREG_FCARG1a || Z_REG(var_use_addr) == ZREG_R0) {
6425 if (Z_REG(var_use_addr) == ZREG_FP) {
6426 | mov T1, Ra(Z_REG(var_use_addr)) // save
6432 if (Z_REG(var_use_addr) != ZREG_FP) {
6433 | mov Ra(Z_REG(var_use_addr)), T1 // restore
6509 if (Z_REG(op1_addr) != ZREG_FP) {
6510 | mov T1, Ra(Z_REG(op1_addr)) // save
6513 if (Z_REG(op1_addr) != ZREG_FP) {
6514 | mov Ra(Z_REG(op1_addr)), T1 // restore
6589 if (Z_REG(op1_addr) != ZREG_FP) {
6590 | mov T1, Ra(Z_REG(op1_addr)) // save
6593 if (Z_REG(op1_addr) != ZREG_FP) {
6594 | mov Ra(Z_REG(op1_addr)), T1 // restore
6606 if (Z_REG(op1_addr) != ZREG_FCARG1a || Z_OFFSET(op1_addr) != 0) {
6723 if (Z_REG(op1_addr) != ZREG_FP) {
6724 | mov T1, Ra(Z_REG(op1_addr)) // save
6737 if (Z_REG(op1_addr) != ZREG_FP) {
6738 | mov Ra(Z_REG(op1_addr)), T1 // restore
6863 if (Z_REG(op1_addr) != ZREG_FCARG1a || Z_OFFSET(op1_addr) != 0) {
7109 | test Ra(Z_REG(op1_addr)), Ra(Z_REG(op1_addr))
7111 | LONG_OP cmp, Z_REG(op1_addr), op2_addr, r0
7115 | test Ra(Z_REG(op2_addr)), Ra(Z_REG(op2_addr))
7117 | LONG_OP cmp, Z_REG(op2_addr), op1_addr, r0
7722 | SSE_AVX_OP ucomisd, vucomisd, Z_REG(op1_addr), op2_addr
7724 | SSE_AVX_OP ucomisd, vucomisd, Z_REG(op2_addr), op1_addr
8757 | test Ra(Z_REG(op1_addr)), Ra(Z_REG(op1_addr))
8888 if (Z_REG(op1_addr) != ZREG_FCARG1a || Z_OFFSET(op1_addr) != 0) {
9715 if (Z_REG(op1_addr) != ZREG_FCARG1a || Z_OFFSET(op1_addr) != 0) {
9722 ZEND_ASSERT(Z_REG(op1_addr) == ZREG_FP);
9742 if (Z_REG(op1_addr) != ZREG_FCARG1a || Z_OFFSET(op1_addr) != 0) {
10767 if (Z_REG(op1_addr) != ZREG_R0 || Z_OFFSET(op1_addr) != 0) {
11798 if (Z_MODE(op1_addr) == IS_REG && Z_REG(op1_addr) == ZREG_R1) {
11939 || if (Z_REG(val_addr) == ZREG_R1) {
11945 || if (Z_REG(val_addr) != ZREG_R1) {
12178 if (Z_REG(op1_addr) != ZREG_FCARG1a || Z_OFFSET(op1_addr) != 0) {
12234 Z_REG(op1_addr) != ZREG_FCARG1a ||
12273 if (Z_REG(res_addr) != ZREG_FP ||
12370 if (Z_REG(op1_addr) != ZREG_FP) {
12371 | mov T1, Ra(Z_REG(op1_addr)) // save
12385 if (Z_REG(op1_addr) != ZREG_FP) {
12386 | mov Ra(Z_REG(op1_addr)), T1 // restore
12460 if (Z_REG(op1_addr) != ZREG_FCARG1a || Z_OFFSET(op1_addr) != 0) {
12586 if (Z_REG(op1_addr) != ZREG_FCARG1a || Z_OFFSET(op1_addr) != 0) {
12807 | mov cl, byte [Ra(Z_REG(res_addr))+Z_OFFSET(res_addr)+offsetof(zval, u1.v.type)]
12819 if (Z_REG(res_addr) != ZREG_FCARG1a || Z_OFFSET(res_addr) != 0) {
13125 && Z_REG(op1_addr) == ZREG_FP) {
13133 if (Z_REG(op1_addr) != ZREG_FCARG1a || Z_OFFSET(op1_addr) != 0) {
13252 if (Z_REG(prop_addr) != ZREG_FCARG1a || Z_OFFSET(prop_addr) != 0) {
13273 if (Z_REG(prop_addr) != ZREG_FCARG1a || Z_OFFSET(prop_addr) != 0) {
13298 if (Z_REG(prop_addr) != ZREG_FCARG1a || Z_OFFSET(prop_addr) != 0) {
13364 if (Z_REG(res_addr) != ZREG_FP ||
13412 } else if (Z_REG(op1_addr) != ZREG_FCARG1a || Z_OFFSET(op1_addr) != 0) {
13522 && Z_REG(op1_addr) == ZREG_FP) {
13530 if (Z_REG(op1_addr) != ZREG_FCARG1a || Z_OFFSET(op1_addr) != 0) {
13550 if (Z_REG(op1_addr) != ZREG_FCARG1a || Z_OFFSET(op1_addr) != 0) {
13676 if (Z_REG(prop_addr) != ZREG_FCARG1a || Z_OFFSET(prop_addr) != 0) {
13904 && Z_REG(op1_addr) == ZREG_FP) {
13912 if (Z_REG(op1_addr) != ZREG_FCARG1a || Z_OFFSET(op1_addr) != 0) {
13932 if (Z_REG(op1_addr) != ZREG_FCARG1a || Z_OFFSET(op1_addr) != 0) {
14019 …if (Z_MODE(val_addr) != IS_MEM_ZVAL || Z_REG(val_addr) != ZREG_FCARG2a || Z_OFFSET(val_addr) != 0)…
14091 …if (Z_MODE(val_addr) != IS_MEM_ZVAL || Z_REG(val_addr) != ZREG_FCARG2a || Z_OFFSET(val_addr) != 0)…
14249 && Z_REG(op1_addr) == ZREG_FP) {
14257 if (Z_REG(op1_addr) != ZREG_FCARG1a || Z_OFFSET(op1_addr) != 0) {
14277 if (Z_REG(op1_addr) != ZREG_FCARG1a || Z_OFFSET(op1_addr) != 0) {
15143 …if (Z_MODE(op1_addr) != IS_MEM_ZVAL || Z_REG(op1_addr) != ZREG_FCARG1a || Z_OFFSET(op1_addr) != 0)…
15175 | cmp byte [Ra(Z_REG(op1_addr))+Z_OFFSET(op1_addr)+offsetof(zval, u1.v.type)], IS_NULL
15515 if (Z_REG(var_addr) != ZREG_FCARG1a || Z_OFFSET(var_addr) != 0) {
