JIT: Code generation for ROPE_INIT, ROPE_ADD and ROPE_END with STRING operands

Better specialization for packed/hash arrays

- improved packed/hash inference.
- added hash guards for ASSIGN_DIM, ASSIGN_DIM_OP, FETCH_DIM_W* instructions
- more accurate invariant

Better specialization for packed/hash arrays

- improved packed/hash inference.
- added hash guards for ASSIGN_DIM, ASSIGN_DIM_OP, FETCH_DIM_W* instructions
- more accurate invariant type guards motion
- invariant packed/hash guards motion
- rename MAY_BE_ARRAY_HASH into MAY_BE_ARRAY_NUMERIC_HASH and add MAY_BE_ARRAY_STRING_HASH
- cleanup

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Fixed conditional jump on uninitialised value (Zend/tests/match/028.phpt failure with function JIT)

Fixed incorrect condition

JIT: Use zend_hash_index_lookup() instead of zend_hash_index_add_new(EG(uninitialized_zval))

Remove leading underscore for _zend_hash_find_known_hash (#7260)

Convert zend_hash_find_ex(..., 1) to zend_hash_find_known_hash(...)
Convert zend_hash_find_ex(..., 0) to zend_hash_find(.

Remove leading underscore for _zend_hash_find_known_hash (#7260)

Convert zend_hash_find_ex(..., 1) to zend_hash_find_known_hash(...)
Convert zend_hash_find_ex(..., 0) to zend_hash_find(...)

Also add serializable changes to UPGRADING.INTERNALS summary

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Implement readonly properties

Add support for readonly properties, for which only a single
initializing assignment from the declaring scope is allowed.

RFC: https://wiki.php.net

Implement readonly properties

Add support for readonly properties, for which only a single
initializing assignment from the declaring scope is allowed.

RFC: https://wiki.php.net/rfc/readonly_properties_v2

Closes GH-7089.

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Deprecate autovivification on false

Deprecate automatically converting "false" into an empty array
on write operands. Autovivification continues to be supported
for "null" values, as

Deprecate autovivification on false

Deprecate automatically converting "false" into an empty array
on write operands. Autovivification continues to be supported
for "null" values, as well as undefined/uninitialized values.

RFC: https://wiki.php.net/rfc/autovivification_false

Closes GH-7131.

Co-authored-by: Tyson Andre <tysonandre775@hotmail.com>
Co-authored-by: Nikita Popov <nikita.ppv@gmail.com>

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JIT/ARM64: Fixed incorrect trace linking.

JIT/ARM64: Fixed possible incorrect exception catching in function JIT.

JIT/AArch64: Support shifted immediate (#7165)

* JIT/AArch64: Support shifted immediate

As pointed out by MikePall in [1], shifted immediate value is supported.
See [2]. For exa

JIT/AArch64: Support shifted immediate (#7165)

* JIT/AArch64: Support shifted immediate

As pointed out by MikePall in [1], shifted immediate value is supported.
See [2]. For example, `add x0, x1, #4096` would be encoded by DynASM
into `add x0, x1, #1, lsl #12` directly.

In this patch, a helper is added to check whether an immediate value is
in the two allowed ranges: (1) 0 to 4095, and (2) LSL #12 on all the
values from the first range.

Note that this helper works for add/adds/sub/subs/cmp/cmn instructions.

[1] https://github.com/LuaJIT/LuaJIT/pull/718
[2]
https://github.com/LuaJIT/LuaJIT/blob/v2.1/dynasm/dasm_arm64.lua#L342

Change-Id: I4870048b9b8e6c429b73a4803af2a3b2d5ec0fbb

* Deprecatd CMP_IMM/ADD_SUB_IMM and add test cases

Macros CMP_IMM and ADD_SUB_IMM are deprecated and instead we use
this helper to guard the immediate encoding.

Add two 64-bit only test cases, since 64-bit integers are used
and tested inside.

Change-Id: I0b42d4617b40372e2f4ce5b6ad31a4ddb7d89e49

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JIT/ARM64: Fixed possible incorrect register allocation

JIT/ARM64: Fixed "may be used uninitialized" compilation warning

JIT: Avoid too aggressive loop unrolling

This fixes tests/func/010.phpt failure with tracing JIT on ARM64.

Typo

JIT/ARM64: Remove redundand x86 specific optimization for recursive calls

On ARM64 we always load "func" into REG0

JIT/ARM64: Improve JIT for MOD instruction.

Eliminate x86 specific register constrints (idiv imlicitly used
%eax and %rdx). On ARM64 we use reserved TMP registers.

JIT/AArch64: Use only reserved TMP registers for EG(vm_interrupt) checks.

This removes limitation of REG0 usage for register-allocation.

JIT/AArch64: Use only reserved TMP registers for EG(jit_trace_num) assignment.

This eliminates a need for checking CPU registers used at the entry to a
side trace.

JIT/AArch64: Use 'tbnz/tbz' to check the signedness (#7123)

'tbnz/tbz' instruction can be used to check whether a given W or X
register value is negative or positive.

For exampl

JIT/AArch64: Use 'tbnz/tbz' to check the signedness (#7123)

'tbnz/tbz' instruction can be used to check whether a given W or X
register value is negative or positive.

For example,
```
tst x0, x0
blt >1
```
can be optimized as `tbnz x0, #63, >1`

It's important to note that the jump range of 'tbnz/tbz' is limited, and
it's better NOT to use 'tbnz/tbz' if the target of 'b.cond' is a label
in section .cold_code or a global label, such as the instruction
sequence `tst RETVALw, RETVALw; blt ->trace_halt` at function
zend_jit_trace_exit_stub(), and the instruction sequence `tst REG0,
REG0; blt >7` at function zend_jit_incdec_obj().

Minor updates:
Use macros BW_OP_32_WITH_CONST and GC_ADDREF at function
zend_jit_push_call_frame().

Change-Id: I1597609bdabf55ea2f9d24528e7a037bc3e5c3a1

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JIT/AArch64: Fix codestyle issues (#7125)

Fix codestyle issues, such as aligning comments, changing whitespace to
tab, adding necessary whitespace.

Change-Id: I0c6ae1e5d87a0f683

JIT/AArch64: Fix codestyle issues (#7125)

Fix codestyle issues, such as aligning comments, changing whitespace to
tab, adding necessary whitespace.

Change-Id: I0c6ae1e5d87a0f6832bc776294558d48a9b5d420

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JIT/AArch64: Complete logical_immediate_p() using DynAsm helpers

JIT/AArch64: Use LSL instruction (DynAsm was fixed by
2963214c15de46f35797b87bb3a84a35c2928f01)

JIT/AArch64: Use 'shifted register' if available (#7108)

One shift instruction can be saved if 'shifted register' is used.

It's worth noting that the destination register of previou

JIT/AArch64: Use 'shifted register' if available (#7108)

One shift instruction can be saved if 'shifted register' is used.

It's worth noting that the destination register of previous shift
instruction doesn't hold the shift result any longer now. And we have to
guarantee that 'shifted register' mode is applied to all the use sites
of this destination register.

Besides, several code-style issues are fixed.

Change-Id: I8bcdd092253d342d383732a926512e761e453808

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JIT/AArch64: Optimize add+ldr to ldr (#7109)

This patch is trivial.

Change-Id: I51b8eb5f12446643a53cc569d9398d0941a2f588